Jianmin Zeng

According to our database, Jianmin Zeng authored at least 9 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 10T SRAM with Two Read and Write Modes across Row and Column for CAM Operation and Computing In-Memory.

Zhang Zhang, Zhihao Chen, Sikai Chen, Guangjun Xie, Jianmin Zeng, Gang Liu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2020

DM-IMCA: A dual-mode in-memory computing architecture for general purpose processing.

Jianmin Zeng, Zhang Zhang, Runhao Chen, Shiyue Liang, Tianlin Cao, Zhiyi Yu, Xin Cheng, Guangjun Xie

IEICE Electron. Express, 2020

High frequency and high efficiency DC-DC converter with sensorless adaptive-sizing technique.

Xin Cheng, Wanjing Shao, Yongqiang Zhang, Jianmin Zeng, Zhang Zhang

IEICE Electron. Express, 2020

2019

A 24-bit sigma-delta ADC with configurable chopping scheme.

Li Li, Xu Cheng, Zhang Zhang, Jianmin Zeng, Xiaoyang Zeng

IEICE Electron. Express, 2019

2018

Countering power analysis attacks by exploiting characteristics of multicore processors.

Jianwei Yang, Fan Dai, Jielin Wang, Jianmin Zeng, Zhang Zhang, Jun Han, Xiaoyang Zeng

IEICE Electron. Express, 2018

A 15 W wireless power receiver with an improved full-wave synchronous rectifier.

Chubin Wu, Guangjun Xie, Zhang Zhang, Xin Cheng, Tairan Fei, Jianmin Zeng, Xiaoyang Zeng

IEICE Electron. Express, 2018

A Qi compatible wireless power receiver with integrated full-wave synchronous rectifier.

Chubin Wu, Zhang Zhang, Jianmin Zeng, Xin Cheng, Guangjun Xie

Sci. China Inf. Sci., 2018

2017

A multi-core-based heterogeneous parallel turbo decoder.

Jianmin Zeng, Chubin Wu, Zhang Zhang, Xin Cheng, Guangjun Xie, Jun Han, Xiaoyang Zeng, Zhiyi Yu

IEICE Electron. Express, 2017

Instruction set extension and hardware acceleration for SVM application toward a vector processor.

Yalong Pang, Jun Han, Jianmin Zeng, Yujie Huang, Xiaoyang Zeng

Proceedings of the International SoC Design Conference, 2017