Jianliang Ma

Orcid: 0009-0000-4445-6294

According to our database1, Jianliang Ma authored at least 20 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Low-Light Image Enhancement via Weighted Low-Rank Tensor Regularized Retinex Model.
Proceedings of the 2024 International Conference on Multimedia Retrieval, 2024

2023
Enhancing Low-Light Images: A Variation-based Retinex with Modified Bilateral Total Variation and Tensor Sparse Coding.
Comput. Graph. Forum, October, 2023

Joint Priors-Based Restoration Method for Degraded Images Under Medium Propagation.
Proceedings of the Pattern Recognition and Computer Vision - 6th Chinese Conference, 2023

Joint Edge-Guided and Spectral Transformation Network for Self-supervised X-Ray Image Restoration.
Proceedings of the Artificial Neural Networks and Machine Learning, 2023

2015
MCMG simulator: A unified simulation framework for CPU and graphic GPU.
J. Comput. Syst. Sci., 2015

Analyzing Memory Access on CPU-GPGPU Shared LLC Architecture.
Proceedings of the 14th International Symposium on Parallel and Distributed Computing, 2015

Buffer Filter: A Last-Level Cache Management Policy for CPU-GPGPU Heterogeneous System.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Making GPU Warp Scheduler and Memory Scheduler Synchronization-Aware.
Proceedings of the Cloud Computing and Big Data, 2015

2014
Improve LLC Bypassing Performance by Memory Controller Improvements in Heterogeneous Multicore System.
Proceedings of the 15th International Conference on Parallel and Distributed Computing, 2014

2013
An Energy-Efficient Scheme for STT-RAM L1 Cache.
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013

Phase Based and Application Based Dynamic Encoding Scheme for Multi-level Cell STT-RAM.
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013

2012
Global register alias table: Boosting sequential program on multi-core.
Future Gener. Comput. Syst., 2012

Parallel Speculative Dom-based XML Parser.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Improve GPGPU Latency Hiding with a Hybrid Recovery Stack and a Window Based Warp Scheduling Policy.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

2011
Access Pattern Based Re-reference Interval Table for Last Level Cache.
Proceedings of the 12th International Conference on Parallel and Distributed Computing, 2011

Global Priority Table for Last-Level Caches.
Proceedings of the IEEE Ninth International Conference on Dependable, 2011

2010
Single Thread Program Parallelism with Dataflow Abstracting Thread.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2010

Function Units Sharing between Neighbor Cores in CMP.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2010

Distributed On-Chip Operating System for Network on Chip.
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2009
A Performance Model for Run-Time Reconfigurable Hardware Accelerator.
Proceedings of the Advanced Parallel Processing Technologies, 8th International Symposium, 2009


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