Jianhua Li

Orcid: 0000-0002-7086-7625

Affiliations:

Hefei University of Technology, School of Computer Science and Information, China (PhD 2013)
City University of Hong Kong, Department of Computer Science, Hong Kong (former)
Anqing Normal University, Department of Computer Science and Technology, Anhui, China (former)

According to our database¹, Jianhua Li authored at least 31 papers between 2010 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

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In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2024

Fault-tolerant routing for reliable packet transmission in on-chip networks.

[BibT_eX]

[DOI]

Microelectron. J., 2024

A tree-recursive partitioned multicast mechanism for NoC-based deep neural network accelerator.

[BibT_eX]

[DOI]

Microelectron. J., 2024

2023

Transit ring: bubble flow control for eliminating inter-ring communication congestion.

[BibT_eX]

[DOI]

J. Supercomput., 2023

A transparent virtual channel power gating method for on-chip network routers.

[BibT_eX]

[DOI]

Integr., 2023

2022

WiGRUNT: WiFi-Enabled Gesture Recognition Using Dual-Attention Network.

[BibT_eX]

[DOI]

IEEE Trans. Hum. Mach. Syst., 2022

2020

A Novel Low-Latency Regional Fault-Aware Fault-Tolerant Routing Algorithm for Wireless NoC.

[BibT_eX]

[DOI]

IEEE Access, 2020

2019

Design of Wireless Network on Chip with Priority-Based MAC.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2019

CPCA: An efficient wireless routing algorithm in WiNoC for cross path congestion awareness.

[BibT_eX]

[DOI]

Integr., 2019

Reuse locality aware cache partitioning for last-level cache.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2019

2018

Design of Low-Power WiNoC with Congestion-Aware Wireless Node.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2018

NVLH: Crash-Consistent Linear Hashing for Non-Volatile Memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

2017

Thread Criticality Assisted Replication and Migration for Chip Multiprocessor Caches.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

2015

Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

2014

A Unified Write Buffer Cache Management Scheme for Flash Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Compiler-Assisted STT-RAM-Based Hybrid Cache for Energy Efficient Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Thread Progress Aware Coherence Adaption for Hybrid Cache Coherence Protocols.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2014

Dual partitioning multicasting for high-performance on-chip networks.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2014

2013

Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Cooperating Virtual Memory and Write Buffer Management for Flash-Based Storage Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

Cache coherence enabled adaptive refresh for volatile STT-RAM.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Hybrid nonvolatile disk cache for energy-efficient and high-performance systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

Code Motion for Migration Minimization in STT-RAM Based Hybrid Cache.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

MAC: migration-aware compilation for STT-RAM based hybrid cache in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

TEACA: Thread ProgrEss Aware Coherence Adaption for hybrid coherence protocols.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

2011

STT-RAM based energy-efficiency hybrid cache for CMPs.

[BibT_eX]

[DOI]

Jianhua Li

Chun Jason Xue

Yinlong Xu

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Optimal task allocation on non-volatile memory based hybrid main memory.

[BibT_eX]

[DOI]

Proceedings of the Research in Applied Computation Symposium, 2011

Exploiting set-level write non-uniformity for energy-efficient NVM-based hybrid cache.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2011

ExLRU: a unified write buffer cache management for flash memory.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Embedded Software, 2011

2010

LADPM: Latency-Aware Dual-Partition Multicast Routing for Mesh-Based Network-on-Chips.

[BibT_eX]

[DOI]

Jianhua Li

Chun Jason Xue

Yinlong Xu

Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010

Jianhua Li

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