Jianhang Yang
Orcid: 0009-0007-2862-4893
According to our database1,
Jianhang Yang
authored at least 4 papers
between 2024 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
2024
2025
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2025
A 0.4-V 500-kHz FLL With Reused TDA-Based Calibration and OTA-Accelerated Technique in 65-nm CMOS for Sleep Timer.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2025
2024
Multim. Tools Appl., February, 2024
Microelectron. J., February, 2024
A 8.1-nW, 4.22-kHz, -40-85 °C relaxation oscillator with subthreshold leakage current compensation and forward body bias buffer for low power IoT applications.
Microelectron. J., February, 2024