Jiangyuan Gu

According to our database, Jiangyuan Gu authored at least 15 papers between 2016 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures.

Haojia Hui, Jiangyuan Gu, Xunbo Hu, Shaojun Wei, Shouyi Yin

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2023

TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA.

Mingyang Kou, Jiangyuan Gu, Hailong Yao, Shaojun Wei, Shouyi Yin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

WindMill: A Parameterized and Pluggable CGRA Implemented by DIAG Design Flow.

Haojia Hui, Jiangyuan Gu, Xunbo Hu, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin

CoRR, 2023

RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA.

Qidie Wu, Jiangyuan Gu, Youxu Lin, Boxiao Han, Hongjun He, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

GEML: GNN-based efficient mapping method for large loop applications on CGRA.

Mingyang Kou, Jun Zeng, Boxiao Han, Fei Xu, Jiangyuan Gu, Hailong Yao

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Mixed-granularity parallel coarse-grained reconfigurable architecture.

Jinyi Deng, Linyun Zhang, Lei Wang, Jiawei Liu, Kexiang Deng, Shibin Tang, Jiangyuan Gu, Boxiao Han, Fei Xu, Leibo Liu, Shaojun Wei, Shouyi Yin

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating.

Song Zhang, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs.

Cheng Li, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA.

Mingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2018

Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration.

Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei

IEEE Trans. Parallel Distributed Syst., 2018

A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications.

Shouyi Yin, Peng Ouyang, Shibin Tang, Fengbin Tu, Xiudong Li, Shixuan Zheng, Tianyi Lu, Jiangyuan Gu, Leibo Liu, Shaojun Wei

IEEE J. Solid State Circuits, 2018

2017

Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory.

Shouyi Yin, Xianqing Yao, Tianyi Lu, Dajiang Liu, Jiangyuan Gu, Leibo Liu, Shaojun Wei

IEEE Trans. Parallel Distributed Syst., 2017

Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect.

Jiangyuan Gu, Shouyi Yin, Shaojun Wei

Proceedings of the 54th Annual Design Automation Conference, 2017

Energy-aware loops mapping on multi-vdd CGRAs without performance degradation.

Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Joint Modulo Scheduling and V_dd Assignment for Loop Mapping on Dual- V_dd CGRAs.

Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016