Jiangyi Li
Orcid: 0000-0001-5859-5877
According to our database1,
Jiangyi Li
authored at least 13 papers
between 2014 and 2019.
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Bibliography
2019
A Femto/Pico-Watt Feedforward Leakage Self-Suppression Logic Family in 180 nm to 28 nm Technologies.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
2018
<i>In~Situ</i> and In-Field Technique for Monitoring and Decelerating NBTI in 6T-SRAM Register Files.
IEEE Trans. Very Large Scale Integr. Syst., 2018
An Area-Efficient Microprocessor-Based SoC With an Instruction-Cache Transformable to an Ambient Temperature Sensor and a Physically Unclonable Function.
IEEE J. Solid State Circuits, 2018
Recent advances in in-situ and in-field aging monitoring and compensation for integrated circuits: Invited paper.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
A 0.78-µW 96-Ch. Deep Sub-Vt Neural Spike Processor Integrated with a Nanowatt Power Management Unit.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
2017
Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities.
IEEE J. Solid State Circuits, 2017
A technique to transform 6T-SRAM arrays into robust analog PUF with minimal overhead.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
An area-efficient microcontroller with an instruction-cache transformable to an ambient temperature sensor and a physically unclonable function.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
Ultra-Compact and Robust Physically Unclonable Function Based on Voltage-Compensated Proportional-to-Absolute-Temperature Voltage Generators.
IEEE J. Solid State Circuits, 2016
Triple-mode photovoltaic power management: Achieving high efficiency against harvesting and load variability.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A 3.07μm<sup>2</sup>/bitcell physically unclonable function with 3.5% and 1% bit-instability across 0 to 80°C and 0.6 to 1.2V in a 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015
Energy-optimal voltage model supporting a wide range of nodal switching rates for early design-space exploration.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
2014
Robust and In-Situ Self-Testing Technique for Monitoring Device Aging Effects in Pipeline Circuits.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014