Jianghua Wan

According to our database1, Jianghua Wan authored at least 17 papers between 2010 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
FT-Matrix: A Coordination-Aware Architecture for Signal Processing.
IEEE Micro, 2014

2013
Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures.
IEICE Trans. Inf. Syst., 2013

Breaking the performance bottleneck of sparse matrix-vector multiplication on SIMD processors.
IEICE Electron. Express, 2013

Decoupled iteration mapping: improving dependency-loop performance on SIMD processors.
IEICE Electron. Express, 2013

Real-Time Implementation of 4x4 MIMO-OFDM System for 3GPP-LTE Based on a Programmable Processor.
Proceedings of the Computer Engineering and Technology - 17th CCF Conference, 2013

Redefining the relationship between scalar and parallel units in SIMD architectures.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012
A cost conscious performance model for media processors.
IEICE Electron. Express, 2012

Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures.
IEEE Comput. Archit. Lett., 2012

Architectural Implications for SIMD Processors in the Wireless Communication Domain.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

2011
LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs.
IEICE Electron. Express, 2011

Matrix Odd-Even Partition: A High Power-Efficient Solution to the Small Grain Data Shuffle.
Proceedings of the Sixth International Conference on Networking, Architecture, and Storage, 2011

AIFSP: An Adaptive Instruction Flow Stream Processor.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Design and chip implementation of a heterogeneous multi-core DSP.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
YHFT-QDSP: High-Performance Heterogeneous Multi-Core DSP.
J. Comput. Sci. Technol., 2010


  Loading...