Jiangfeng Wu

According to our database1, Jiangfeng Wu authored at least 53 papers between 1997 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A 0.5-V 0.02% THD Bulk-Driven OTA for Continuous-Time Applications in 180 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024

A Foreground Wide-Band Receiver I/Q Mismatch Calibration Method in FDD Transceiver.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2024

Design and Implementation of an EMI-Immune Daisy Chain Interface With a PID-Based CDR Algorithm for Battery Management System Communication.
IEEE Access, 2024

A 40Gb/s Multi-band Wireline Receiver Analog Front-end for 50.4dB Channel Loss Compensation.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

2023
A Wideband Receiver I/Q Mismatch Calibration Method in FDD Transceiver.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Foreground LSB-Based Capacitor Mismatch Calibration Method in An 18-bit SAR ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 4.75-64 Gb/s PAM-4 Wireline Transmitter with 3-tap FFE in 28-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Low-power Digital Automatic Gain Control Design in Wireless Communication Receivers.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A low-power daisy-chain controller implemention in BMS based on power mode switching.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

Pipelined-SAR ADC Calibration Technique Based on Gain-Bit Weights.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

Complexity-Reduced Joint Calibration for Nonlinearity and I/Q Imbalance in Direct-Conversion Transmitters.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A 32GS/s 7bit TI-SAR ADC in 28nm for 32Gb/s ADC-Based SerDes Receiver.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
A Current-Mode, 30 dB Range with 0.5 dB Step, 0.1 to 6 GHz Attenuator for Wideband Receiver.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A 64Gb/s PAM-4 Digital Equalizer With Tap-Configurable FFE and Partially Unrolled DFE in 28nm CMOS.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

0.7-6 GHz Programable Gain Push-Pull Driver PA Based on Dual-Loop Biases.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
A 71dB DC Gain, 0.1% THD, 0.5-V Bulk-Driven Class-AB OTA Achieved by Novel CMFB Methods.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A 32Gb/s NRZ Wireline Transmitter with CMFB- Based CML Driver in 28nm CMOS Technology.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A 2-GS/s 200-MHz BW Oversampling Continuous-Time Pipeline ADC with Adaptive Digital Filter in 28nm.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A 161mW 32Gb/s ADC-Based NRZ SerDes Receiver Front End in 28nm.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

An Input Buffer for 4 GS/s 14-b Time-Interleaved ADC.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A 6-bit Active Phase Shifter with Quadrature Outputs.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

Digital Calibration of Capacitor Mismatch and Gain Error in Pipelined SAR ADCs.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

Physical Coding Sublayer For 32Gbps SerDes Based On JESD204C.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2019
A Double-Latch Comparator for Multi-GS/s SAR ADCs in 28nm CMOS.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

An Area-Efficient Multi-Rate Digital Decimator.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

High Linear Ring Amplifier Design with Analysis on Settling Procedures.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
A 5-Bit 500-MS/s Asynchronous Digital Slope ADC With Two Comparators.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 12GS/s 6-bit DAC with 4-2 Segmentation in 40nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Duty Cycle Distortion in Half-rate Nyquist DACs with Limited Output Bandwidth.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Session 21 - Analog techniques II.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver.
IEEE J. Solid State Circuits, 2016

27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Scattering phenomenology of arctic lake ice.
Proceedings of the 2016 IEEE International Geoscience and Remote Sensing Symposium, 2016

Intelligent battery management for electric and hybrid electric vehicles: A survey.
Proceedings of the IEEE International Conference on Industrial Technology, 2016

2015
Microwave Backscatter From Arctic Lake Ice and Polarimetric Implications.
IEEE Trans. Geosci. Remote. Sens., 2015

A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS.
IEEE J. Solid State Circuits, 2015



2014
Super-miniaturized borehole antenna design and radio-wave estimation of sub-surface hydraulic fractures at MF band.
Proceedings of the 2014 IEEE Geoscience and Remote Sensing Symposium, 2014

2013
A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization.
IEEE J. Solid State Circuits, 2013

Radio-wave detection and estimation of sub-surface hydraulic fractures at MF band.
Proceedings of the 2013 IEEE International Geoscience and Remote Sensing Symposium, 2013

2012
A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm<sup>2</sup> and 500 mW in 40 nm Digital CMOS.
IEEE J. Solid State Circuits, 2012

A 40 nm CMOS analog front end with enhanced audio for HSPA/EDGE multimedia applications.
Proceedings of the 38th European Solid-State Circuit conference, 2012

A 240mW 2.1GS/s 12b pipeline ADC using MDAC equalization.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Simulation system design of a small-scale unmanned helicopter.
Int. J. Model. Identif. Control., 2011

2008
A 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver for 100m UTP Cable in 0.13μm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006
Electromechanical ΔΣ modulation with high-Q micromechanical accelerometers and pulse density modulated force feedback.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

2004
A low-noise low-offset capacitive sensing amplifier for a 50-μg√Hz monolithic CMOS MEMS accelerometer.
IEEE J. Solid State Circuits, 2004

2001
A simulation study of electromechanical delta-sigma modulators.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Performance of wavelet packet-division multiplexing in impulsive and Gaussian noise.
IEEE Trans. Commun., 2000

Bayesian and Dempster-Shafer target identification for radar surveillance.
IEEE Trans. Aerosp. Electron. Syst., 2000

A Table-Based Time-Domain Simulation Method for Oversampled Microelectromechanical Systems.
Proceedings of the 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, 2000

1997
Wavelet packet division multiplexing and wavelet packet design under timing error effects.
IEEE Trans. Signal Process., 1997


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