Jiang Xu

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

PHANES: ReRAM-based photonic accelerator for deep neural networks.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Reduce Loss and Crosstalk in Integrated Silicon-Photonic Multistage Switching Fabrics Through Multichip Partition.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Simultaneously Tolerate Thermal and Process Variations Through Indirect Feedback Tuning for Silicon Photonic Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Multi-Core Power Management through Deep Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Rejuvenate Post-Moore's Law Computing with Photonics-Electronics Hybrid Systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on IC Design and Technology, 2021

2020

Multidevice Collaborative Power Management Through Decentralized Knowledge Sharing.

[BibT_eX]

[DOI]

Zhongyuan Tian

Haoran Li

IEEE Trans. Very Large Scale Integr. Syst., 2020

Chip-Specific Power Delivery and Consumption Co-Management for Process-Variation-Aware Manycore Systems Using Reinforcement Learning.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Multidomain Inter/Intrachip Silicon Photonic Networks for Energy-Efficient Rack-Scale Computing Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Cross-Layer Optimization Framework for Integrated Optical Switches in Data Centers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Efficient Optical Power Delivery System for Hybrid Electronic-Photonic Manycore Processors.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.

[BibT_eX]

[DOI]

Ibrahim Abe M. Elfadel

Mehran Mozaffari Kermani

IEEE Trans. Very Large Scale Integr. Syst., 2019

Collaborative Power Management Through Knowledge Sharing Among Multiple Devices.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Scalable Low-Power High-Performance Rack-Scale Optical Network.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM Workshop on Photonics-Optics Technology Oriented Networking, 2019

Systematic Exploration of High-Radix Integrated Silicon Photonic Switches for Datacenters.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

2018

A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2018

Workload-Aware Adaptive Power Delivery System Management for Many-Core Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Silicon Photonics for Computing Systems.

[BibT_eX]

[DOI]

Yuichi Nakamura

Andrew B. Kahng

ACM J. Emerg. Technol. Comput. Syst., 2018

A Comprehensive Electro-Optical Model for Silicon Photonic Switches.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Decentralized Collaborative Power Management through Multi-Device Knowledge Sharing.

[BibT_eX]

[DOI]

Zhongyuan Tian

Haoran Li

Jun Feng

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Co-manage power delivery and consumption for manycore systems using reinforcement learning.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

RSON: An inter/intra-chip silicon photonic network for rack-scale computing systems.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Multi-device collaborative management through knowledge sharing.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Editorial.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Energy-Efficient Power Delivery System Paradigms for Many-Core Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Thermal-sensitive design and power optimization for a 3D torus-based optical NoC.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse Distance.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Adaptive power delivery system management for many-core processors with on/off-chip voltage regulators.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

MOCA: an Inter/Intra-Chip Optical Network for Memory.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Modular reinforcement learning for self-adaptive energy efficiency optimization in multicore system.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Improve Chip Pin Performance Using Optical Interconnects.

[BibT_eX]

[DOI]

Haoran Li

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2016

Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations.

[BibT_eX]

[DOI]

Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016

JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models.

[BibT_eX]

[DOI]

Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2016

2015

An Inter/Intra-Chip Optical Network for Manycore Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

An Improved Content-Based Music Recommending Method with Weighted Tags.

[BibT_eX]

[DOI]

Proceedings of the MultiMedia Modeling - 21st International Conference, 2015

Memory Access Analysis of Many-core System with Abundant Bandwidth.

[BibT_eX]

[DOI]

Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Adaptively tolerate power-gating-induced power/ground noise under process variations.

[BibT_eX]

[DOI]

Zhifei Wang

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Coherent crosstalk noise analyses in ring-based optical interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Alleviate chip I/O pin constraints for multicore processors through optical interconnects.

[BibT_eX]

[DOI]

Xiaowen Wu

Yaoyao Ye

Qinfen Hao

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

SUOR: Sectioned Undirectional Optical Ring for Chip Multiprocessor.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2014

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2014

A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Des. Test, 2014

Introduction to the special session on "Silicon photonic interconnects: an illusion or a realistic solution?".

[BibT_eX]

[DOI]

Sébastien Le Beux

Yvain Thonnart

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

CLAP: a crosstalk and loss analysis platform for optical interconnects.

[BibT_eX]

[DOI]

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A systematic network-on-chip traffic modeling and generation methodology.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2013

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8).

[BibT_eX]

[DOI]

NII Shonan Meet. Rep., 2013

A formal study on topology and floorplan characteristics of mesh and torus-based optical networks-on-chip.

[BibT_eX]

[DOI]

Kai Feng

Yaoyao Ye

Microprocess. Microsystems, 2013

System-level analysis of mesh-based hybrid optical-electronic network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2012

2011

Power Gating Aware Task Scheduling in MPSoC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Satisfiability Modulo Graph Theory for Task Mapping and Scheduling on Multiprocessor Systems.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2011

Novel RD-Optimized VBSME With Matching Highly Data Re-Usable Hardware Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2011

Coroutine-Based Synthesis of Efficient Embedded Software From SystemC Models.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2011

Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A NoC Traffic Suite Based on Real Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Sub-pixel downsampling of video with matching highly data re-use hardware architecture.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

A new distributed congestion control mechanism for networks on chip.

[BibT_eX]

[DOI]

Telecommun. Syst., 2010

UNION: A unified inter/intra-chip optical network for chip multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

A Hierarchical Hybrid Optical-Electronic Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A highly data reusable and standard-compliant motion estimation hardware architecture.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE International Conference on Multimedia and Expo, 2010

Crosstalk noise and bit error rate analysis for optical network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs.

[BibT_eX]

[DOI]

Wei Zhang

IEEE Micro, 2009

Efficient algorithms for 2D area management and online task placement on runtime reconfigurable FPGAs.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2009

Efficient Software Synthesis for Dynamic Single Appearance Scheduling of Synchronous Dataflow.

[BibT_eX]

[DOI]

Weichen Liu

Zonghua Gu

IEEE Embed. Syst. Lett., 2009

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A Novel Multiple Description Video Coding based on H.264/AVC Video Coding Standard.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip.

[BibT_eX]

[DOI]

Huaxi Gu

Wei Zhang

Proceedings of the Design, Automation and Test in Europe, 2009

An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

A case study of on-chip sensor network in multiprocessor system-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Compilers, 2009

3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC).

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008

ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip.

[BibT_eX]

[DOI]

Huaxi Gu

Zheng Wang

Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

A novel optical mesh network-on-chip for gigascale systems-on-chip.

[BibT_eX]

[DOI]

Huaxi Gu

Zheng Wang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2006

A design methodology for application-specific networks-on-chip.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2006

2005

A Methodology for Architectural Design of Multimedia Multiprocessor SoCs.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2005

A methodology for design, modeling, and analysis of networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

H.264 HDTV Decoder Using Application-Specific Networks-On-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005

2004

A Case Study in Networks-on-Chip Design for Embedded Video.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

2003

Augmenting Platform-Based Design with Synthesis Tools.

[BibT_eX]

[DOI]

Yuan Xie

J. Circuits Syst. Comput., 2003

A wave-pipelined on-chip interconnect structure for networks-on-chips.

[BibT_eX]

[DOI]

Proceedings of the 11th Annual IEEE Symposium on High Performance Interconnects, 2003

2002

Wave pipelining for application-specific networks-on-chips.

[BibT_eX]

[DOI]