Jiang Nan
Orcid: 0000-0002-8854-3055
According to our database1,
Jiang Nan
authored at least 9 papers
between 2001 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
A Diode-Enhanced Scheme for Giant Magnetoresistance Amplification and Reconfigurable Logic.
IEEE Access, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
2017
Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
2016
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
2008
Proceedings of the International Conference on Computer Science and Software Engineering, 2008
Proceedings of the International Conference on Computer Science and Software Engineering, 2008
Proceedings of the International Conference on Computer Science and Software Engineering, 2008
2001
Robust guaranteed cost control with H<sub>∞</sub>-γ disturbance attenuation performance.
Proceedings of the American Control Conference, 2001