Jiang Hu

Orcid: 0009-0005-8842-7811

According to our database1, Jiang Hu authored at least 313 papers between 1999 and 2024.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2016, "For contributions to gate, interconnect, and clock network optimization in VLSI circuits".

Timeline

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Bibliography

2024
MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

Distributed hypothesis testing for large dimensional two-sample mean vectors.
Stat. Comput., December, 2024

Two-sample test of stochastic block models.
Comput. Stat. Data Anal., April, 2024

Toward Fully Automated Machine Learning for Routability Estimator Development.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

Adaptive online continual multi-view learning.
Inf. Fusion, March, 2024

Riemannian Natural Gradient Methods.
SIAM J. Sci. Comput., February, 2024

A novel prediction model construction and result interpretation method for slope deformation of deep excavated expansive soil canals.
Expert Syst. Appl., February, 2024

Approximate controllability and optimal control in fractional differential equations with multiple delay controls, fractional Brownian motion with Hurst parameter in 0H12, and Poisson jumps.
Commun. Nonlinear Sci. Numer. Simul., January, 2024

Convergence Analysis of an Adaptively Regularized Natural Gradient Method.
IEEE Trans. Signal Process., 2024

MA-SAM: Modality-agnostic SAM adaptation for 3D medical image segmentation.
Medical Image Anal., 2024

A projected semismooth Newton method for a class of nonconvex composite programs with strong prox-regularity.
J. Mach. Learn. Res., 2024

The limiting spectral distribution of large random permutation matrices.
J. Appl. Probab., 2024

NextPolish2: A Repeat-aware Polishing Tool for Genomes Assembled Using HiFi Long Reads.
Genom. Proteom. Bioinform., 2024

A multilevel optimization approach for daily scheduling of combined heat and power units with integrated electrical and thermal storage.
Expert Syst. Appl., 2024

PatternPaint: Generating Layout Patterns Using Generative AI and Inpainting Techniques.
CoRR, 2024

Nonconvex Federated Learning on Compact Smooth Submanifolds With Heterogeneous Data.
CoRR, 2024

AdaFish: Fast low-rank parameter-efficient fine-tuning by using second-order information.
CoRR, 2024

MinBLoG: Minimization of Boolean Logic Functions using Graph Attention Network.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

Flip-Flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

Identifying Smart Contract Security Issues in Code Snippets from Stack Overflow.
Proceedings of the 33rd ACM SIGSOFT International Symposium on Software Testing and Analysis, 2024

Aiding Microprocessor Performance Validation with Machine Learning.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2024

Decentralized Non-Smooth Optimization Over the Stiefel Manifold.
Proceedings of the 13th IEEE Sensor Array and Multichannel Signal Processing Workshop, 2024

Composite Federated Learning with Heterogeneous Data.
Proceedings of the IEEE International Conference on Acoustics, 2024

DiMO-Sparse: Differentiable Modeling and Optimization of Sparse CNN Dataflow and Hardware Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
GNN-Based Hierarchical Annotation for Analog Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

A spatiotemporal identification method for deformation characteristics of expansive soil canal slope based on spectral clustering.
Expert Syst. Appl., September, 2023

Examining the impacts of fitness app features on user well-being.
Inf. Manag., July, 2023

Exact and approximate computation of critical values of the largest root test in high dimension.
Commun. Stat. Simul. Comput., May, 2023

The Dark Side: Security and Reliability Concerns in Machine Learning for EDA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

Performance-driven Wire Sizing for Analog Integrated Circuits.
ACM Trans. Design Autom. Electr. Syst., March, 2023

T2T-YAO: A Telomere-to-Telomere Assembled Diploid Reference Genome for Han Chinese.
Genom. Proteom. Bioinform., 2023

Radiology-Llama2: Best-in-Class Large Language Model for Radiology.
CoRR, 2023

Securing Cloud FPGAs Against Power Side-Channel Attacks: A Case Study on Iterative AES.
CoRR, 2023

Achieving Consensus over Compact Submanifolds.
CoRR, 2023

Decentralized Weakly Convex Optimization Over the Stiefel Manifold.
CoRR, 2023

Machine Learning for Microprocessor Performance Bug Localization.
CoRR, 2023

Decentralized Riemannian natural gradient methods with Kronecker-product approximations.
CoRR, 2023

Early Identification of Timing Critical RTL Components using ML based Path Delay Prediction.
Proceedings of the 5th ACM/IEEE Workshop on Machine Learning for CAD, 2023

Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Scaled Population Division for Approximate Computing.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Invited Paper: The Inevitability of AI Infusion Into Design Closure and Signoff.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Systolic Array Placement on FPGAs.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Privacy Policy and Hosts' Concerns on Accommodation Sharing Platforms.
Proceedings of the 56th Hawaii International Conference on System Sciences, 2023

Lightning Talk: Power and Performance Reconciliation - from Tradeoff to Win-Win.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Special Session: Machine Learning for Embedded System Design.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023

Application of Engineering Cost Database to Modern Power Plant Management.
Proceedings of the IEEE International Symposium on Broadband Multimedia Systems and Broadcasting, 2023

BufFormer: A Generative ML Framework for Scalable Buffering.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Rethink before Releasing Your Model: ML Model Extraction Attack in EDA.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Toward Taming the Overhead Monster for Data-flow Integrity.
ACM Trans. Design Autom. Electr. Syst., 2022

Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction.
IEEE Trans. Emerg. Top. Comput., 2022

Preplacement Net Length and Timing Estimation by Customized Graph Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Dynamic prediction of life-threatening events for patients in intensive care unit.
BMC Medical Informatics Decis. Mak., 2022

CLT for linear spectral statistics of high-dimensional sample covariance matrices in elliptical distributions.
J. Multivar. Anal., 2022

The application of machine learning and deep learning in sport: predicting NBA players' performance and popularity.
J. Inf. Telecommun., 2022

Construction and Optimization of Green Supply Chain Management Mode of Agricultural Enterprises in the Digital Economy.
Int. J. Inf. Syst. Supply Chain Manag., 2022

Machine-Learning Based Delay Prediction for FPGA Technology Mapping.
Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022

Double Deep Q-Learning Based Irrigation and Chemigation Control.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Transaction Level Stimulus Optimization in Functional Verification Using Machine Learning Predictors.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Global Placement Exploiting Soft 2D Regularity.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

DEEP: Developing Extremely Efficient Runtime On-Chip Power Meters.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Robustify ML-Based Lithography Hotspot Detectors.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Deep Learning Toolkit-Accelerated Analytical Co-Optimization of CNN Hardware and Dataflow.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Are Analytical Techniques Worthwhile for Analog IC Placement?
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Towards collaborative intelligence: routability estimation based on decentralized private data.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Mapping Large Scale Finite Element Computing on to Wafer-Scale Engines.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Examining the Role of Privacy Policy on Host Information Disclosure on Accommodation Sharing Platforms.
Proceedings of the 28th Americas Conference on Information Systems, 2022

2021
FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation.
ACM Trans. Design Autom. Electr. Syst., 2021

Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

SeFAct2: Selective Feature Activation for Energy-Efficient CNNs Using Optimized Thresholds.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Field-derived relationships between fish habitat distribution and flow-sediment conditions in fluctuating backwater zone of the Three Gorges Reservoir.
Ecol. Informatics, 2021

ALIGN: A System for Automating Analog Layout.
IEEE Des. Test, 2021

A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing.
Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021

APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Machine Learning Techniques in Analog Layout Automation.
Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Automatic Routability Predictor Development Using Neural Architecture Search.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Automatic Microprocessor Performance Bug Detection.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Analog Layout Generation using Optimized Primitives.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Research on Identification of Power Grid Weakness Based on Bayesian Inference.
Proceedings of CECNet 2021, 2021

Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Three-User Cooperative NOMA Transmission.
IEEE Wirel. Commun. Lett., 2020

Breaking Analog Locking Techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Polynomial Regression and Measurement Error: Implications for Information Systems Research.
Data Base, 2020

Fast IR Drop Estimation with Machine Learning.
CoRR, 2020

NextPolish: a fast and efficient genome polishing tool for long-read assembly.
Bioinform., 2020

Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits.
Proceedings of the IEEE International Test Conference, 2020

Exploring a Machine Learning Approach to Performance Driven Analog IC Placement.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Learning from Experience: Applying ML to Analog Circuit Design.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

How Much Does Regularity Help FPGA Placement?
Proceedings of the International Conference on Field-Programmable Technology, 2020

Scaled Population Subtraction for Approximate Computing.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Predicting National Basketball Association Players Performance and Popularity: A Data Mining Approach.
Proceedings of the Computational Collective Intelligence - 12th International Conference, 2020

Fast IR Drop Estimation with Machine Learning : Invited Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Routing-Free Crosstalk Prediction.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

A Customized Graph Neural Network Model for Guiding Analog IC Placement.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

When Hosts Disclose Their Private Information on Accommodation Sharing Platforms: An Information Commercialization Perspective.
Proceedings of the 53rd Hawaii International Conference on System Sciences, 2020

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Scaled Population Arithmetic for Efficient Stochastic Computing.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Enhancing Generalization of Wafer Defect Detection by Data Discrepancy-aware Preprocessing and Contrast-varied Augmentation.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Examining the Impacts of Fitness App Functionalities.
Proceedings of the 26th Americas Conference on Information Systems, 2020

2019
Central Limit Theorem for Mutual Information of Large MIMO Systems With Elliptically Correlated Channels.
IEEE Trans. Inf. Theory, 2019

Zoned safety monitoring model for uplift pressures of concrete dams.
Trans. Inst. Meas. Control, 2019

EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Dynamic Approximation of JPEG Hardware.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

An Analytical Approach for Error PMF Characterization in Approximate Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Structured Quasi-Newton Methods for Optimization with Orthogonality Constraints.
SIAM J. Sci. Comput., 2019

Impact of the usage of social media in the workplace on team and employee performance.
Inf. Manag., 2019

Detecting Common Method Bias: Performance of the Harman's Single-Factor Test.
Data Base, 2019

Improving QoS for Global Dual-Criticality Scheduling on Multiprocessors.
Proceedings of the 25th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2019

Breaking Analog Locking Techniques via Satisfiability Modulo Theories.
Proceedings of the IEEE International Test Conference, 2019

Fast Mapping-Based High-Level Synthesis of Pipelined Circuits.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A Memory-Efficient Markov Decision Process Computation Framework Using BDD-based Sampling Representation.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

ALIGN: Open-Source Analog Layout Automation from the Ground Up.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Layout recognition attacks on split manufacturing.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

SeFAct: selective feature activation and early classification for CNNs.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Error Analysis and Optimization in Approximate Arithmetic Circuits.
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

2018
A Simple Yet Efficient Accuracy-Configurable Adder Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018

The Cat and Mouse in Split Manufacturing.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Built-In Self-Test and In Situ Analog Circuit Optimization Platform.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Adaptive Quadratically Regularized Newton Method for Riemannian Optimization.
SIAM J. Matrix Anal. Appl., 2018

Multi-scale performance simulation and effect analysis for hydraulic concrete submitted to leaching and frost.
Eng. Comput., 2018

NextSV: a meta-caller for structural variants from low-coverage long-read sequencing data.
BMC Bioinform., 2018

Simultaneous Wireless Information and Power Transfer in Cellular Two-Way Relay Networks With Massive MIMO.
IEEE Access, 2018

Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems.
Proceedings of the 26th International Conference on Real-Time Networks and Systems, 2018

Interconnect Optimization Considering Multiple Critical Paths.
Proceedings of the 2018 International Symposium on Physical Design, 2018

Increasing Rate of Diffusion of Innovation in Supply Chain: Targeting the Early Adopters in UK Supply Chain.
Proceedings of the Advances in Production Management Systems. Smart Manufacturing for Industry 4.0, 2018

DUCER: a Fast and Lightweight Error Correction Scheme for In-Vehicle Network Communication.
Proceedings of the 2018 IEEE International Conference on Vehicular Electronics and Safety, 2018

Analyzing Accessed Content Sequences with HDP-based Models.
Proceedings of the 3rd International Conference on Multimedia Systems and Signal Processing, 2018

Using imprecise computing for improved non-preemptive real-time scheduling.
Proceedings of the 55th Annual Design Automation Conference, 2018

Experience on Consumer Purchasing Decision-making: a Study of Anchoring Effects.
Proceedings of the 24th Americas Conference on Information Systems, 2018

Analyze the Factors of Firms to Rely on Internal and External Suppliers.
Proceedings of the 24th Americas Conference on Information Systems, 2018

Exploring Serverless Computing for Neural Network Training.
Proceedings of the 11th IEEE International Conference on Cloud Computing, 2018

2017
A comparative study on neural network-based prediction of smart community energy consumption.
Proceedings of the 2017 IEEE SmartWorld, 2017

Thwarting analog IC piracy via combinational locking.
Proceedings of the IEEE International Test Conference, 2017

A Reliable Soil Moisture Sensing Methodology for Agricultural Irrigation.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Reinforcement Learning Control for Water-Efficient Agricultural Irrigation.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Enhancing Datacenter Resource Management through Temporal Logic Constraints.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Front-end-of-line attacks in split manufacturing.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Making split fabrication synergistically secure and manufacturable.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits.
Proceedings of the 54th Annual Design Automation Conference, 2017

A quantifiable approach to approximate computing: special session.
Proceedings of the 2017 International Conference on Compilers, 2017

Fast and Highly Scalable Bayesian MDP on a GPU Platform.
Proceedings of the 8th ACM International Conference on Bioinformatics, 2017

Routing perturbation for enhanced security in split manufacturing.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Polynomial Regression and Measurement Error: Implications for IS Research.
Proceedings of the 23rd Americas Conference on Information Systems, 2017

2016
Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory.
ACM Trans. Design Autom. Electr. Syst., 2016

Dam structural behavior identification and prediction by using variable dimension fractal model and iterated function system.
Appl. Soft Comput., 2016

Proximity Optimization for Adaptive Circuit Design.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

Control synthesis and delay sensor deployment for efficient ASV designs.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

The cat and mouse in split manufacturing.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Optimal design of JPEG hardware under the approximate computing paradigm.
Proceedings of the 53rd Annual Design Automation Conference, 2016

GPU acceleration for Bayesian control of Markovian genetic regulatory networks.
Proceedings of the 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2016

2015
Proximity Sensing Based on a Dynamic Vision Sensor for Mobile Devices.
IEEE Trans. Ind. Electron., 2015

Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Built-In Self Optimization for Variation Resilience of Analog Filters.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Having your cake and eating it too: Energy savings without performance loss through resource sharing driven power management.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Collaborative gate implementation selection and adaptivity assignment for robust combinational circuits.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

A pre-search assisted ILP approach to analog integrated circuit routing.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

GPU acceleration for PCA-based statistical static timing analysis.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Timing verification for adaptive integrated circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Joint precision optimization and high level synthesis for approximate computing.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Regularity-constrained floorplanning for multi-core processors.
Integr., 2014

STORM: A Simple Traffic-Optimized Router Microarchitecture for Networks-on-Chip.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Case studies on variation tolerant and low power design using planar asymmetric double gate transistor.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Algorithms for power-efficient QoS in application specific NoCs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
Dual-Level Adaptive Supply Voltage System for Variation Resilience.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Boostable Repeater Design for Variation Resilience in VLSI Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2013

In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches.
ACM Trans. Design Autom. Electr. Syst., 2013

Guest editorial: Special section on cross-domain physical optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Multifractal scaling behavior analysis for existing dams.
Expert Syst. Appl., 2013

Resource allocation algorithms for guaranteed service in application-specific NoCs.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Power gating with block migration in chip-multiprocessor last-level caches.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Dynamic voltage and frequency scaling for shared resources in multicore processor designs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Guest Editorial Special Section on the 2011 International Symposium on Physical Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A node scheduling based on partition for WSN.
Proceedings of the 2012 Wireless Telecommunications Symposium, 2012

Track assignment considering crosstalk-induced performance degradation.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

A low overhead built-in delay testing with voltage and frequency adaptation for variation resilience.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

2011
Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies.
VLSI Design, 2011

GPU-Based Parallelization for Fast Circuit Optimization.
ACM Trans. Design Autom. Electr. Syst., 2011

Simultaneous Technology Mapping and Placement for Delay Minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A mean shift based small target tracking algorithm in colored video.
Proceedings of the Third International Conference of Soft Computing and Pattern Recognition, 2011

Transient and fine-grained voltage adaptation for variation resilience in VLSI interconnects.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Lagrangian relaxation for gate implementation selection.
Proceedings of the 2011 International Symposium on Physical Design, 2011

A bilinear interpolation mean shift small target tracking algorithm.
Proceedings of the 5th International Conference on Signal Processing and Communication Systems, 2011

Gate sizing and device technology selection algorithms for high-performance industrial designs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
Combinatorial Algorithms for Fast Clock Mesh Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2010

An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Pattern Sensitive Placement Perturbation for Manufacturability.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Useful clock skew optimization under a multi-corner multi-mode design framework.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Accurate clock mesh sizing via sequential quadraticprogramming.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Clustering-based simultaneous task and voltage scheduling for NoC systems.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal.
Proceedings of the Design, Automation and Test in Europe, 2010

Detecting tangled logic structures in VLSI netlists.
Proceedings of the 47th Design Automation Conference, 2010

Physical design techniques for optimizing RTA-induced variations.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Clock Buffer Polarity Assignment for Power Noise Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Gate Sizing for Cell-Library-Based Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A fast general slew constrained minimum cost buffering algorithm.
Microelectron. J., 2009

A single layer zero skew clock routing in X architecture.
Sci. China Ser. F Inf. Sci., 2009

Impact of lithography-friendly circuit layout.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008
Buffering in the Layout Environment.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Timing-Driven Interconnect Synthesis.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Buffer Insertion Basics.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Power Grid Analysis and Optimization Using Algebraic Multigrid.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Robust Clock Tree Routing in the Presence of Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Buffering Interconnect for Multicore Processor Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Zero skew clock routing in X-architecture based on an improved greedy matching algorithm.
Integr., 2008

ASIC design flow considering lithography-induced effects.
IET Circuits Devices Syst., 2008

Low Power Gated Clock Tree Driven Placement.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Elastic Timing Scheme for Energy-Efficient and Robust Performance.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Activity and register placement aware gated clock network design.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Multi-scenario buffer insertion in multi-core processor designs.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Gate planning during placement for gated clock network.
Proceedings of the 26th International Conference on Computer Design, 2008

Delay-optimal simultaneous technology mapping and placement with applications to timing optimization.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Built-In Proactive Tuning System for Circuit Aging Resilience.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Low power clock buffer planning methodology in F-D placement for large scale circuit design.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Handling partial correlations in yield prediction.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Integrated Placement and Skew Optimization for Rotary Clocking.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Utilizing Redundancy for Timing Critical Interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Wire Sizing and Spacing for Lithographic Printability and Timing Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Path-Based Buffer Insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Guest Editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Fast Algorithms for Slew-Constrained Minimum Cost Buffering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A Placement Methodology for Robust Clocking.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

An Efficient Algorithm for RLC Buffer Insertion.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Pattern sensitive placement for manufacturability.
Proceedings of the 2007 International Symposium on Physical Design, 2007

The influence of user tailoring and cognitive load on user performance in spoken dialogue systems.
Proceedings of the 8th Annual Conference of the International Speech Communication Association, 2007

Modeling, optimization and control of rotary traveling-wave oscillator.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Unified adaptivity optimization of clock and logic signals.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Context & usability testing: user-modeled information presentation in easy and difficult driving conditions.
Proceedings of the 2007 Conference on Human Factors in Computing Systems, 2007

A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Antenna Avoidance in Layer Assignment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Analytical bound for unwanted clock skew due to wire width variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Reducing clock skew variability via crosslinks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Accurate estimation of global buffer delay within a floorplan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Low Power Trellis Decoder with Overscaled Supply Voltage.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

An Improved AMG-based Method for Fast Power Grid Analysis.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Efficient Model Update for General Link-Insertion Networks.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Statistical clock tree routing for robustness to process variations.
Proceedings of the 2006 International Symposium on Physical Design, 2006

High performance clock routing in X-architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Fast decap allocation based on algebraic multigrid.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A new RLC buffer insertion algorithm.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Integrated placement and skew optimization for rotary clocking.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Associative skew clock routing for difficult instances.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Steiner network construction for timing critical nets.
Proceedings of the 43rd Design Automation Conference, 2006

Standard cell characterization considering lithography induced variations.
Proceedings of the 43rd Design Automation Conference, 2006

Adaptive language behavior in HCI: how expectations and beliefs about a system affect users' word choice.
Proceedings of the 2006 Conference on Human Factors in Computing Systems, 2006

groupTime: preference based group scheduling.
Proceedings of the 2006 Conference on Human Factors in Computing Systems, 2006

2005
An efficient merging scheme for prescribed skew clock routing.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Navigating Register Placement for Low Power Clock Network Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Natural Language Interface Put in Perspective: Interaction of Search Method and Task Complexity.
Proceedings of the Natural Language Understanding and Cognitive Science, 2005

Coupling aware timing optimization and antenna avoidance in layer assignment.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Improved algorithms for link-based non-tree clock networks for skew variability reduction.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Natural Language Query vs. Keyword Search: Effects of Task Complexity on Search Performance, Participant Perceptions, and Preferences.
Proceedings of the Human-Computer Interaction, 2005

Preference-Based Group Scheduling.
Proceedings of the Human-Computer Interaction, 2005

DiCER: distributed and cost-effective redundancy for variation tolerance.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Practical techniques to reduce skew and its variations in buffered clock networks.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Navigating registers in placement for clock network minimization.
Proceedings of the 42nd Design Automation Conference, 2005

Timing driven track routing considering coupling capacitance.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Skew scheduling and clock routing for improved tolerance to process variations.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Register placement for low power clock network.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Making fast buffer insertion even faster via approximation techniques.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Clock network minimization methodology based on incremental placement.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Library cell layout with Alt-PSM compliance and composability.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A methodology for the simultaneous design of supply and signal networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Porosity-aware buffered Steiner tree construction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Buffered Clock Tree for High Quality IC Design.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Exploiting level sensitive latches in wire pipelining.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Reducing clock skew variability via cross links.
Proceedings of the 41th Design Automation Conference, 2004

Fast and flexible buffer trees that navigate the physical layout environment.
Proceedings of the 41th Design Automation Conference, 2004

Layer assignment for crosstalk risk minimization.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A place and route aware buffered Steiner tree construction.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Buffer insertion with adaptive blockage avoidance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

A practical methodology for early buffer and wire resource allocation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Process variation aware clock tree routing.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Porosity aware buffered steiner tree construction.
Proceedings of the 2003 International Symposium on Physical Design, 2003

A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
Performance Driven Global Routing Through Gradual Refinement.
VLSI Design, 2002

A timing-constrained simultaneous global routing algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Congestion-driven codesign of power and signal networks.
Proceedings of the 39th Design Automation Conference, 2002

2001
Steiner tree optimization for buffers, blockages, and bays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A survey on multi-net global routing for integrated circuits.
Integr., 2001

Buffered Steiner trees for difficult instances.
Proceedings of the 2001 International Symposium on Physical Design, 2001

2000
Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999
Non-Hanan routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model.
Proceedings of the 1999 International Symposium on Physical Design, 1999

FAR-DS: Full-Plane AWE Routing with Driver Sizing.
Proceedings of the 36th Conference on Design Automation, 1999


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