Jianfeng Zhu

Orcid: 0000-0002-0485-8034

Affiliations:
  • Tsinghua University, Beijing, China


According to our database1, Jianfeng Zhu authored at least 31 papers between 2011 and 2024.

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Bibliography

2024
A High-Performance Genomic Accelerator for Accurate Sequence-to-Graph Alignment Using Dynamic Programming Algorithm.
IEEE Trans. Parallel Distributed Syst., February, 2024

UpWB: An Uncoupled Architecture Design for White-box Cryptography Using Vectorized Montgomery Multiplication.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

CATCAM: a 28 nm constant-time alteration TCAM enabling less than 50 ns update latency.
Sci. China Inf. Sci., 2024

Harp: Leveraging Quasi-Sequential Characteristics to Accelerate Sequence-to-Graph Mapping of Long Reads.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
GEM: Ultra-Efficient Near-Memory Reconfigurable Acceleration for Read Mapping by Dividing and Predictive Scattering.
IEEE Trans. Parallel Distributed Syst., December, 2023

QuickFPS: Architecture and Algorithm Co-Design for Farthest Point Sampling in Large-Scale Point Clouds.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

M2STaR: A Multimode Spatio-Temporal Redundancy Design for Fault-Tolerant Coarse-Grained Reconfigurable Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

CASA: An Energy-Efficient and High-Speed CAM-based SMEM Seeding Accelerator for Genome Alignment.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Shogun: A Task Scheduling Framework for Graph Mining Accelerators.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

MapZero: Mapping for Coarse-grained Reconfigurable Architectures with Reinforcement Learning and Monte-Carlo Tree Search.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

Orinoco: Ordered Issue and Unordered Commit with Non-Collapsible Queues.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2022
Dynamic-II Pipeline: Compiling Loops With Irregular Branches on Static-Scheduling CGRA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

An energy-efficient dynamically reconfigurable cryptographic engine with improved power/EM-side-channel-attack resistance.
Sci. China Inf. Sci., 2022

CaSMap: agile mapper for reconfigurable spatial architectures by automatically clustering intermediate representations and scattering mapping process.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

Software Defined Chips - Volume I, 2
Springer, ISBN: 978-981-19-6993-5, 2022

2021
An Elastic Task Scheduling Scheme on Coarse-Grained Reconfigurable Architectures.
IEEE Trans. Parallel Distributed Syst., 2021

Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters.
IEEE J. Solid State Circuits, 2021

2020
Pattern-Based Dynamic Compilation System for CGRAs With Online Configuration Transformation.
IEEE Trans. Parallel Distributed Syst., 2020

A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications.
ACM Comput. Surv., 2020

2019
Jintide®: A Hardware Security Enhanced Server CPU with Xeon® Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Processor.
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

A General Pattern-Based Dynamic Compilation Framework for Coarse-Grained Reconfigurable Architectures.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2016
TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions.
IEEE Trans. Parallel Distributed Syst., 2016

2015
A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Acceleration of control flows on reconfigurable architecture with a composite method.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2013
Low-Power Reconfigurable Processor Utilizing Variable Dual V<sub>DD</sub>.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

2011
Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect.
J. Electron. Test., 2011

A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect.
J. Electron. Test., 2011

A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011


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