Jianfeng Zhu

According to our database, Jianfeng Zhu authored at least 31 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

A High-Performance Genomic Accelerator for Accurate Sequence-to-Graph Alignment Using Dynamic Programming Algorithm.

Gang Zeng, Jianfeng Zhu, Yichi Zhang, Ganhui Chen, Zhenhai Yuan, Shaojun Wei, Leibo Liu

IEEE Trans. Parallel Distributed Syst., February, 2024

UpWB: An Uncoupled Architecture Design for White-box Cryptography Using Vectorized Montgomery Multiplication.

Xiangren Chen, Bohan Yang, Jianfeng Zhu, Jun Liu, Shuying Yin, Guang Yang, Min Zhu, Shaojun Wei, Leibo Liu

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

CATCAM: a 28 nm constant-time alteration TCAM enabling less than 50 ns update latency.

Chenchen Deng, Tianzhu Xiong, Zhaoshi Li, Zhiwei Liu, Yao Wang, Jianfeng Zhu, Jun Yang, Shaojun Wei, Leibo Liu

Sci. China Inf. Sci., 2024

Harp: Leveraging Quasi-Sequential Characteristics to Accelerate Sequence-to-Graph Mapping of Long Reads.

Yichi Zhang, Dibei Chen, Gang Zeng, Jianfeng Zhu, Zhaoshi Li, Longlong Chen, Shaojun Wei, Leibo Liu

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023

GEM: Ultra-Efficient Near-Memory Reconfigurable Acceleration for Read Mapping by Dividing and Predictive Scattering.

Longlong Chen, Jianfeng Zhu, Guiqiang Peng, Mingxu Liu, Shaojun Wei, Leibo Liu

IEEE Trans. Parallel Distributed Syst., December, 2023

QuickFPS: Architecture and Algorithm Co-Design for Farthest Point Sampling in Large-Scale Point Clouds.

Meng Han, Liang Wang, Limin Xiao, Hao Zhang, Chenhao Zhang, Xiangrong Xu, Jianfeng Zhu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

M2STaR: A Multimode Spatio-Temporal Redundancy Design for Fault-Tolerant Coarse-Grained Reconfigurable Architectures.

Xiangyu Kong, Jianfeng Zhu, Xingchen Man, Guihuan Song, Yi Huang, Chenchen Deng, Pengfei Gou, Shouyi Yin, Shaojun Wei, Leibo Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

CASA: An Energy-Efficient and High-Speed CAM-based SMEM Seeding Accelerator for Genome Alignment.

Yi Huang, Lingkun Kong, Dibei Chen, Zhiyu Chen, Xiangyu Kong, Jianfeng Zhu, Konstantinos Mamouras, Shaojun Wei, Kaiyuan Yang, Leibo Liu

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Shogun: A Task Scheduling Framework for Graph Mining Accelerators.

Yibo Wu, Jianfeng Zhu, Wenrui Wei, Longlong Chen, Liang Wang, Shaojun Wei, Leibo Liu

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

MapZero: Mapping for Coarse-grained Reconfigurable Architectures with Reinforcement Learning and Monte-Carlo Tree Search.

Xiangyu Kong, Yi Huang, Jianfeng Zhu, Xingchen Man, Yang Liu, Chunyang Feng, Pengfei Gou, Minggui Tang, Shaojun Wei, Leibo Liu

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

Orinoco: Ordered Issue and Unordered Commit with Non-Collapsible Queues.

Dibei Chen, Tairan Zhang, Yi Huang, Jianfeng Zhu, Yang Liu, Pengfei Gou, Chunyang Feng, Binghua Li, Shaojun Wei, Leibo Liu

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2022

Dynamic-II Pipeline: Compiling Loops With Irregular Branches on Static-Scheduling CGRA.

Baofen Yuan, Jianfeng Zhu, Xingchen Man, Zijiao Ma, Shouyi Yin, Shaojun Wei, Leibo Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

An energy-efficient dynamically reconfigurable cryptographic engine with improved power/EM-side-channel-attack resistance.

Chenchen Deng, Min Zhu, Jinjiang Yang, Youyu Wu, Jiaji He, Bohan Yang, Jianfeng Zhu, Shouyi Yin, Shaojun Wei, Leibo Liu

Sci. China Inf. Sci., 2022

CaSMap: agile mapper for reconfigurable spatial architectures by automatically clustering intermediate representations and scattering mapping process.

Xingchen Man, Jianfeng Zhu, Guihuan Song, Shouyi Yin, Shaojun Wei, Leibo Liu

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Upward Packet Popup for Deadlock Freedom in Modular Chiplet-Based Systems.

Yibo Wu, Liang Wang, Xiaohang Wang, Jie Han, Jianfeng Zhu, Honglan Jiang, Shouyi Yin, Shaojun Wei, Leibo Liu

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

Software Defined Chips - Volume I, 2

Shaojun Wei, Leibo Liu, Jianfeng Zhu, Chenchen Deng

Springer, ISBN: 978-981-19-6993-5, 2022

2021

An Elastic Task Scheduling Scheme on Coarse-Grained Reconfigurable Architectures.

Longlong Chen, Jianfeng Zhu, Yangdong Deng, Zhaoshi Li, Jian Chen, Xiaowei Jiang, Shouyi Yin, Shaojun Wei, Leibo Liu

IEEE Trans. Parallel Distributed Syst., 2021

Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters.

Jianfeng Zhu, Ao Luo, Guanhua Li, Bowei Zhang, Yong Wang, Gang Shan, Yi Li, Jianfeng Pan, Chenchen Deng, Shouyi Yin, Shaojun Wei, Leibo Liu

IEEE J. Solid State Circuits, 2021

2020

Pattern-Based Dynamic Compilation System for CGRAs With Online Configuration Transformation.

Leibo Liu, Xingchen Man, Jianfeng Zhu, Shouyi Yin, Shaojun Wei

IEEE Trans. Parallel Distributed Syst., 2020

A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications.

Leibo Liu, Jianfeng Zhu, Zhaoshi Li, Yanan Lu, Yangdong Deng, Jie Han, Shouyi Yin, Shaojun Wei

ACM Comput. Surv., 2020

2019

Jintide®: A Hardware Security Enhanced Server CPU with Xeon® Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Processor.

Leibo Liu, Ao Luo, Guanhua Li, Jianfeng Zhu, Yong Wang, Gang Shan, Jianfeng Pan, Shouyi Yin, Shaojun Wei

Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

A General Pattern-Based Dynamic Compilation Framework for Coarse-Grained Reconfigurable Architectures.

Xingchen Man, Leibo Liu, Jianfeng Zhu, Shaojun Wei

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2016

TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions.

Leibo Liu, Junbin Wang, Jianfeng Zhu, Chenchen Deng, Shouyi Yin, Shaojun Wei

IEEE Trans. Parallel Distributed Syst., 2016

2015

A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels.

Jianfeng Zhu, Leibo Liu, Shouyi Yin, Xiao Yang, Shaojun Wei

IEEE Trans. Very Large Scale Integr. Syst., 2015

A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only).

Junbin Wang, Leibo Liu, Jianfeng Zhu, Shouyi Yin, Shaojun Wei

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Acceleration of control flows on reconfigurable architecture with a composite method.

Junbin Wang, Leibo Liu, Jianfeng Zhu, Shouyi Yin, Shaojun Wei

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA.

Jianfeng Zhu, Liyang Pan, Yaru Yan, Dong Wu, Hu He

IEEE Trans. Very Large Scale Integr. Syst., 2014

2013

Low-Power Reconfigurable Processor Utilizing Variable Dual V_DD.

Jianfeng Zhu, Leibo Liu, Shouyi Yin, Shaojun Wei

IEEE Trans. Circuits Syst. II Express Briefs, 2013

2011

Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect.

Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan

J. Electron. Test., 2011

A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect.

Jianfeng Zhu, Hu He, Dong Wu, Liyang Pan

J. Electron. Test., 2011

A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only).

Jianfeng Zhu, Dong Wu, Yaru Yan, Xiao Yu, Hu He, Liyang Pan

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011