Jianfeng Gao

Affiliations:
  • Chinese Academy of Sciences, Institute of Microelectronics, Beijing, China


According to our database1, Jianfeng Gao authored at least 9 papers between 2020 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Transport mechanism in Hf0.5Zr0.5O2-based ferroelectric diodes.
Sci. China Inf. Sci., December, 2023

Implementation of 16 Boolean logic operations based on one basic cell of spin-transfer-torque magnetic random access memory.
Sci. China Inf. Sci., June, 2023

A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023

First Demonstration of a Design Methodology for Highly Reliable Operation at High Temperature on 128kb 1T1C FeRAM Chip.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

16-layer 3D Vertical RRAM with Low Read Latency (18ns), High Nonlinearity (>5000) and Ultra-low Leakage Current (~pA) Self-Selective Cells.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Nano-scaled transistor reliability characterization at nano-second regime.
Sci. China Inf. Sci., 2021

2020
A ReRAM-Based Computing-in-Memory Convolutional-Macro With Customized 2T2R Bit-Cell for AIoT Chip IP Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020


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