Jianfei Wang

According to our database, Jianfei Wang authored at least 17 papers between 2023 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering.

Zihang Wang, Yushu Yang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang

IEEE Trans. Very Large Scale Integr. Syst., February, 2025

A High-Throughput and Flexible CNN Accelerator Based on Mixed-Radix FFT Method.

Yishuo Meng, Junfeng Wu, Siwei Xiang, Jianfei Wang, Jia Hou, Zhijie Lin, Chen Yang

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2025

A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption.

Jianfei Wang, Chen Yang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Leibo Liu

IEEE Trans. Circuits Syst. II Express Briefs, January, 2025

An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm.

Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang

IEEE Trans. Circuits Syst. II Express Briefs, January, 2025

Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted Data.

Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

A Lightweight and Efficient Encryption/Decryption Coprocessor for RLWE-Based Cryptography.

Yushu Yang, Zihang Wang, Jianfei Wang, Jia Hou, Yang Su, Chen Yang

IEEE Trans. Circuits Syst. II Express Briefs, December, 2024

A Novel Two-Level Protection Scheme against Hardware Trojans on a Reconfigurable CNN Accelerator.

Zichu Liu, Jia Hou, Jianfei Wang, Chen Yang

Cryptogr., September, 2024

ALSCA: A Large-Scale Sparse CNN Accelerator Using Position-First Dataflow and Input Channel Merging Approach.

Yishuo Meng, Siwei Xiang, Jianfei Wang, Jia Hou, Chen Yang

IEEE Trans. Circuits Syst. II Express Briefs, July, 2024

A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture.

Jianfei Wang, Chen Yang, Fahong Zhang, Jia Hou, Yishuo Meng, Siwei Xiang, Yang Su

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units.

Chen Yang, Yaoyao Yang, Yishuo Meng, Kaibo Huo, Siwei Xiang, Jianfei Wang, Li Geng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024

WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks.

Chen Yang, Yishuo Meng, Jiawei Xi, Siwei Xiang, Jianfei Wang, Kuizhi Mei

IEEE Trans. Very Large Scale Integr. Syst., January, 2024

A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm.

Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Siwei Xiang, Yang Su

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024

An Efficient and Scalable FHE-Based PDQ Scheme: Utilizing FFT to Design a Low Multiplication Depth Large-Integer Comparison Algorithm.

Fahong Zhang, Chen Yang, Rui Zong, Xinran Zheng, Jianfei Wang, Yishuo Meng

IEEE Trans. Inf. Forensics Secur., 2024

2023

An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling Workflow.

Yishuo Meng, Chen Yang, Siwei Xiang, Jianfei Wang, Kuizhi Mei, Li Geng

IEEE Trans. Very Large Scale Integr. Syst., October, 2023

TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm.

Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Yang Su

IEEE Trans. Very Large Scale Integr. Syst., August, 2023

POSS-CNN: An Automatically Generated Convolutional Neural Network with Precision and Operation Separable Structure Aiming at Target Recognition and Detection.

Jia Hou, Jingyu Zhang, Qi Chen, Siwei Xiang, Yishuo Meng, Jianfei Wang, Cimang Lu, Chen Yang

Inf., 2023

An Efficient Hardware Implementation of Dilated Convolution Using a Novel Channel-Equivalent Decomposition Method.

Yuheng Xia, Yishuo Meng, Siwei Xiang, Jianfei Wang, Chen Yang

Proceedings of the IEEE International Conference on Integrated Circuits, 2023