Jianfei Jiang

Orcid: 0000-0002-5521-6197

Affiliations:

Shanghai Jiao Tong University, Department of Microelectronics, China (PhD 2017)

According to our database¹, Jianfei Jiang authored at least 62 papers between 2011 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2024

A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance.

[BibT_eX]

[DOI]

Expert Syst. Appl., 2024

A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Compact Powers-of-Two: An Efficient Non-Uniform Quantization for Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Enabling Multiple Tensor-wise Operator Fusion for Transformer Models on Spatial Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

Exploiting bit sparsity in both activation and weight in neural networks accelerators.

[BibT_eX]

[DOI]

Integr., 2023

RTMDet-R2: An Improved Real-Time Rotated Object Detector.

[BibT_eX]

[DOI]

Proceedings of the Pattern Recognition and Computer Vision - 6th Chinese Conference, 2023

A Hierarchical Communication Algorithm for Distributed Deep Learning Training.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE International Conference on Computer Design, 2023

Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

An Efficient near-Bank Processing Architecture for Personalized Recommendation System.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

An NoC-based CNN Accelerator for Edge Computing.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

High-Performance Genomic Analysis Heterogeneous System Using OpenCL.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2022

A CPU-FPGA Heterogeneous Acceleration System for Scene Text Detection Network.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images.

[BibT_eX]

[DOI]

IEEE Geosci. Remote. Sens. Lett., 2022

Boosting ReRAM-based DNN by Row Activation Oversubscription.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Fast FPGA-Based Emulation for ReRAM-Enabled Deep Neural Network Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A Mapping Method for Reconfigurable Array based on Decoupled DataFlow.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International Conference on Big Data Security on Cloud, 2021

A CPU-FPGA Based Heterogeneous Accelerator for RepVGG.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

An Efficient Massive MIMO Detector Based on Second-Order Richardson Iteration: From Algorithm to Flexible Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Priority Branches for Ship Detection in Optical Remote Sensing Images.

[BibT_eX]

[DOI]

Remote. Sens., 2020

Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Frequency Attention Network: Blind Noise Removal for Real Images.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ACCV 2020 - 15th Asian Conference on Computer Vision, Kyoto, Japan, November 30, 2020

2019

A New Cellular-Based Redundant TSV Structure for Clustered Faults.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A New Approximate Multiplier Design for Digital Signal Processing.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Deploying and Optimizing Convolutional Neural Networks on Heterogeneous Architecture.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2017

Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC.

[BibT_eX]

[DOI]

Integr., 2017

A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS.

[BibT_eX]

[DOI]

Integr., 2017

A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An on-chip circuit for timing measurement of SRAM IP.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A metastability-based true random number generator on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Parallel SER analysis for combinational and sequential standard cell circuits.

[BibT_eX]

[DOI]

Weiguang Sheng

Jianfei Jiang

Zhigang Mao

Microelectron. J., 2016

Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2016

2015

Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Design optimization for capacitive-resistively driven on-chip global interconnect.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

A contactless testing methodology for pre-bond interposer.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A crosstalk avoidance scheme based on re-layout of signal TSV.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013

Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Design of a high voltage stimulator chip for a stroke rehabilitation system.

[BibT_eX]

[DOI]

Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

2012

A pre-emphasis circuit design for high speed on-chip global interconnect.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011

A clock-less transceiver for global interconnect.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A novel low power 64-kb SRAM using bit-lines charge-recycling and non-uniform cell scheme.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

An efficient 90nm technology-node GHz transceiver of on-chip global interconnect.

[BibT_eX]

[DOI]

Zaixiao Zheng

Zhigang Mao

Jianfei Jiang

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A new asynchronous delay-insensitive link based on a 1-of-4 LETS code.

[BibT_eX]

[DOI]

Can Wang

Qin Wang

Jianfei Jiang

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Jianfei Jiang

Timeline

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