Jiandong Zang

Orcid: 0009-0004-9843-5340

According to our database¹, Jiandong Zang authored at least 3 papers between 2020 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Timeline

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PhD thesis

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Bibliography

2024

An 8 GHz Semi-Digital DLL for CDR in High Speed SerDes Receivers.

[BibT_eX]

[DOI]

Yi Ding

Jiandong Zang

Jun Liu

Proceedings of the 2024 5th International Conference on Computing, 2024

2021

A Low-Area and Low-Power Comma Detection and Word Alignment Circuits for JESD204B/C Controller.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

A 5-13.5 Gb/s Multistandard Receiver With High Jitter Tolerance Digital CDR in 40-nm CMOS Process.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Jiandong Zang

Timeline

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