Jianbo Dong

Orcid: 0000-0003-0939-8943

According to our database1, Jianbo Dong authored at least 21 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Boosting Large-scale Parallel Training Efficiency with C4: A Communication-Driven Approach.
CoRR, 2024

Crux: GPU-Efficient Communication Scheduling for Deep Learning Training.
Proceedings of the ACM SIGCOMM 2024 Conference, 2024

2023
Flor: An Open High Performance RDMA Framework Over Heterogeneous RNICs.
Proceedings of the 17th USENIX Symposium on Operating Systems Design and Implementation, 2023

Enabling Switch Memory Management for Distributed Training with In-Network Aggregation.
Proceedings of the IEEE INFOCOM 2023, 2023

2022
Lamda: The Last Mile of the Datacenter Network Does matter.
CoRR, 2022

Libra: In-network Gradient Aggregation for Speeding up Distributed Sparse Deep Training.
CoRR, 2022

PICASSO: Unleashing the Potential of GPU-centric Training for Wide-and-deep Recommender Systems.
Proceedings of the 38th IEEE International Conference on Data Engineering, 2022

SPACE-2: Tree-Structured Semi-Supervised Contrastive Pre-training for Task-Oriented Dialog Understanding.
Proceedings of the 29th International Conference on Computational Linguistics, 2022

2021
ACCL: Architecting Highly Scalable Distributed Training Systems With Highly Efficient Collective Communication Library.
IEEE Micro, 2021

2020
Dissecting the Communication Latency in Distributed Deep Sparse Learning.
Proceedings of the IMC '20: ACM Internet Measurement Conference, 2020

EFLOPS: Algorithm and System Co-Design for a High Performance Distributed Training Platform.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2018
Venice: An Effective Resource Sharing Architecture for Data Center Servers.
ACM Trans. Comput. Syst., 2018

2016
Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Venice: Exploring server architectures for effective resource sharing.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

P-Socket: optimizing a communication library for a PCIe-based intra-rack interconnect.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Adapting Memory Hierarchies for Emerging Datacenter Interconnects.
J. Comput. Sci. Technol., 2015

2013
Cost effective data center servers.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2011
Wear rate leveling: lifetime enhancement of PRAM with endurance variation.
Proceedings of the 48th Design Automation Conference, 2011

2010
Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling.
J. Syst. Archit., 2010

Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009


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