Jianan Wen

Orcid: 0009-0003-7733-8907

According to our database1, Jianan Wen authored at least 7 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024

Towards Reliable and Energy-Efficient RRAM Based Discrete Fourier Transform Accelerator.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins.
Proceedings of the High Performance Computing, 2023

LUT-based RRAM Model for Neural Accelerator Circuit Simulation.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

2022
Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021
Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including Assessment.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2020
Low-Cost DNN Hardware Accelerator for Wearable, High-Quality Cardiac Arrythmia Detection.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020


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