Jianan Mu

Orcid: 0000-0001-8513-0792

According to our database1, Jianan Mu authored at least 8 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
TensorTEE: Unifying Heterogeneous TEE Granularity for Efficient Secure Collaborative Tensor Computing.
CoRR, 2024

Efficient Functional Safety Method for Gate-Level Fine-Grained Digital Circuits with ISO-26262.
Proceedings of the IEEE International Test Conference in Asia, 2024

Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants.
Proceedings of the IEEE European Test Symposium, 2023

Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022
A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022


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