Jian Yan

Orcid: 0000-0001-5400-4611

Affiliations:
  • Fudan University, State Key Laboratory of ASIC and System, Shanghai, China


According to our database1, Jian Yan authored at least 6 papers between 2012 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2017
Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2015
An adaptive cross-layer fault recovery solution for reconfigurable SoCs.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

UniStream: A unified stream architecture combining configuration and data processing.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014
Design space exploration for FPGA-based hybrid multicore architecture.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

2013
SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model.
IEEE Trans. Very Large Scale Integr. Syst., 2013

2012
A partially reconfigurable architecture supporting hardware threads.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012


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