Jian Wang

Affiliations:

Ericsson, Mobile Broadband Software Design, Ottawa, ON, Canada
Nortel Montréal Laboratory, Montreal, QC, Canada (1997 - 2009)
Technology University of Vienna, Austria (former)
INRIA-Rocquencourt, France (former)
Tsinghua University, Department of Computer Science and Technology, Beijing, China (former)

According to our database¹, Jian Wang authored at least 28 papers between 1987 and 2021.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2021

Using machine learning techniques for DSP software performance prediction at source code level.

[BibT_eX]

[DOI]

Connect. Sci., 2021

2019

Comparing DSP Software Performance Prediction Models at Source Code Level - From Analytical to Statistical.

[BibT_eX]

[DOI]

J. Softw., 2019

2017

Software performance prediction at source level.

[BibT_eX]

[DOI]

Erh-Wen Hu

Bogong Su

Jian Wang

Proceedings of the 15th IEEE International Conference on Software Engineering Research, 2017

2006

New DSP Benchmark based on Selectable Mode Vocoder (SMV).

[BibT_eX]

Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

2004

Software De-Pipelining Technique.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2004), 2004

Loop optimization with tradeoff between cycle count and code size for DSP applications.

[BibT_eX]

[DOI]

Proceedings of the 2004 12th European Signal Processing Conference, 2004

2003

De-pipeline a software-pipelined loop.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

2000

A scalable loop optimization approach for scalable DSP processors.

[BibT_eX]

[DOI]

Jian Wang

Bogong Su

Erh-Wen Hu

Proceedings of the IEEE International Conference on Acoustics, 2000

1999

Source-level loop optimization for DSP code generation.

[BibT_eX]

[DOI]

Bogong Su

Jian Wang

Andrew Esguerra

Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

1998

Software pipelining of nested loops for real-time DSP applications.

[BibT_eX]

[DOI]

Jian Wang

Bogong Su

Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

1997

A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors.

[BibT_eX]

[DOI]

Rad Silvera

Jian Wang

Ramaswamy Govindarajan

Guang R. Gao

Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997

1996

Pipelining-Dovetailing: A Transformation to Enhance Software Pipelining for Nested Loops.

[BibT_eX]

[DOI]

Jian Wang

Guang R. Gao

Proceedings of the Compiler Construction, 6th International Conference, 1996

1995

Trace software pipelining.

[BibT_eX]

[DOI]

Jian Wang

Andreas Krall

M. Anton Ertl

J. Comput. Sci. Technol., 1995

Decomposed software pipelining with reduced register requirement.

[BibT_eX]

[DOI]

Jian Wang

Andreas Krall

M. Anton Ertl

Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

1994

Using timed Petri net to model instruction-level loop scheduling with resource constraints.

[BibT_eX]

[DOI]

Jian Wang

Christine Eisenbeis

Bogong Su

J. Comput. Sci. Technol., 1994

Decomposed software pipelining: A new perspective and a new approach.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 1994

Software pipelining with register allocation and spilling.

[BibT_eX]

[DOI]

Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

A study of pointer aliasing for software pipelining using run-time disambiguation.

[BibT_eX]

[DOI]

Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

Trace Software Pipelining: A Novel Technique for Parallelization of Loops with Branches.

[BibT_eX]

[DOI]

Proceedings of the Parallel Architectures and Compilation Techniques, 1994

1993

URPR-1: A single-chip VLIW architecture.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1993

Decomposed Software Pipelining: A New Approach to Exploit Instruction Level Parallelism for Loop Programs.

[BibT_eX]

[DOI]

Jian Wang

Christine Eisenbeis

Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993

1992

Foresighted Instruction Scheduling Under Timing Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1992

1991

GURPR<sup>*</sup>: A New Global Software Pipelining Algorithm.

[BibT_eX]

[DOI]

Bogong Su

Jian Wang

Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

1990

A software pipelining based VLIW architecture and optimizing compiler.

[BibT_eX]

[DOI]

Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990

1988

Global microcode compaction under timing constraints.

[BibT_eX]

[DOI]

Bogong Su

Jian Wang

Jinshi Xia

Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28, 1988

The Architecture of a Distributed Knowledge Base System.

[BibT_eX]

Proceedings of the IFIP TC2/TC8/WG 2.6/WG 8.1 Working Conference on the Role of Artificial Intelligence in Databases and Information Systems, 1988

1987

GURPR - a method for global software pipelining.

[BibT_eX]

[DOI]

Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987

Microcode compaction with timing constraints.

[BibT_eX]

[DOI]

Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987

Jian Wang

Timeline

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