Jian Wang

Affiliations:
  • Fudan University, School of Microelectronics, State Key Lab of ASIC & System, Shanghai, China


According to our database1, Jian Wang authored at least 40 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., June, 2024

An optimized EEGNet processor for low-power and real-time EEG classification in wearable brain-computer interfaces.
Microelectron. J., 2024

A new model for parametrically evaluating the routability of GRM FPGA.
IEICE Electron. Express, 2024

2022
AutoTEA: An Automated Transistor-level Efficient and Accurate design tool for FPGA design.
Integr., 2022

An Effective Test Method for Block RAMs in Heterogeneous FPGAs Based on a Novel Partial Bitstream Relocation Technique.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
AutoTEA: Automated Transistor-level Efficient and Accurate Optimization for GRM FPGA Design.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020
FABLE-DTS: Hardware-Software Co-Design of a Fast and Stable Data Transmission System for FPGAs.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

A Tile-based Interconnect Model for FPGA Architecture Exploration.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

FPTLOPT: An Automatic Transistor-Level Optimization Tool for GRM FPGA.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

INTB: A New FPGA Interconnect Model for Architecture Exploration.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019
An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

An Analytical-based Hybrid Algorithm for FPGA Placement.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Research on the impact of different benchmark circuits on the representative path in FPGAs.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

Design and implementation of Serial ATA pbysical layer on FPGA.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

An FPGA-based log-structure Flash memory system for space exploration.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Low-delay Configurable Register for FPGA.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

An Exponential Dynamic Weighted Fair Queuing Algorithm for Task Scheduling in Chip Verification Platform.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

A Web-based Waveform Viewer for BR0101 Chip Testing Platform.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Design of a power efficient self-adaptive LVDS driver.
IEICE Electron. Express, 2018

A SA-based parallel method for FPGA placement.
IEICE Electron. Express, 2018

2017
FPGA-based convolution neural network for traffic sign recognition.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A deep research on the chip verification platform based on network.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
Prototyping design of a flexible DSP block with pipeline structure for FPGA.
IEICE Electron. Express, 2016

A universal automatic on-chip measurement of FPGA's internal setup and hold times.
IEICE Electron. Express, 2016

Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015
A new automatic method for testing interconnect resources in FPGAs based on general routing matrix.
IEICE Electron. Express, 2015

A power efficient current-mode differential driver for FPGAs.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

FPGA bitstream compression and decompression based on LZ77 algorithm and BMC technique.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A FPGA prototype design emphasis on low power technique.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Novel FPGA clock network with low latency and skew (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
A novel net-partition-based multithread FPGA routing method.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A novel multithread routing method for FPGAs (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

The timing control design of 65nm block RAM in FPGA.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Improved unified interconnect unit for high speed and scalable FPGA.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Weight-based FPGA placement algorithm with wire effect considered.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2011
The design and verification of SEU-hardened configurable DFF.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

FPGA interconnect timing library based on the statistical method.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Research on design method of scalable Configurable IP Core.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011


  Loading...