Jian Luo

Orcid: 0000-0001-6738-7199

Affiliations:

University of Electronic Science and Technology of China, The State Key Laboratory of Electronic Thin Films and Integrated Devices, Chengdu, China

According to our database¹, Jian Luo authored at least 7 papers between 2018 and 2020.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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Bibliography

2020

A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

2019

A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2019

A Full-Band Timing Mismatch Calibration Technique in Time-Interleaved ADCs.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2019

A Low Voltage 10-Bit Non-Binary 2B/Cycle Time and Voltage Based SAR ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

The Effects of Comparator Dynamic Capacitor Mismatch in SAR ADC and Correction.

[BibT_eX]

[DOI]

IEEE Access, 2018

A Supply Noise Compensation Circuit for Clock Buffers to Reduce Timing Jitter.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

Jian Luo

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