Jian-Hsing Lee

Orcid: 0000-0001-5903-6890

According to our database1, Jian-Hsing Lee authored at least 23 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Negative Triggering Current Induced the Latch-up in the Circuit without the ESD device to Power.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024

The Influence of the Block Design on the ID-VD Curves of Power Transistor for E-SOA Characterization.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2024

2023
A Concise Electrothermal Model to Characterize the Thermal Safe-Operating Area of Power Transistor.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

Transmission Line Pulse Width Impacting on Device Performances.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

Optimizing Device Metal Routing Layouts by the Simulation Tool.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

Bipolar Transistors' Holding Phenomena.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

2022
Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

EOS Endurance Power Circuits without Depletion Mode Devices.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022

Gate Voltages Impacting on Latch-up Measurements.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022

2021
Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Optimizing Power IC Layouts by Simulation Tools.
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021

Signal Control Switching Applied on Large Array Devices' Layouts.
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021

2020
Signal Control Switching for Improving Large Array Devices' ESD Performances.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

The Correlations between ESD and TLP in Large Array Devices.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

2019
Physical Model for ESD Human Body Model to Transmission Line Pulse.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Tunable Holding-Voltage High Voltage ESD Devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Analyzing Gate-Driven Circuit Parameters for Adding ESD Performances.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019

2015
Printed-circuit board (PCB) charge induced product yield-loss during the final test.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Methodology to achieve planar technology-like ESD performance in FINFET process.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Enhanced CDM-robustness for the packaged IC with the extra bonding wire to the die-attach plate.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Robust ESD self-protected LDNMOSFET by an enhanced displacement-current triggering.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2005
A new pre-driver design for improving the ESD performance of the high voltage tolerant I/O.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2002
The embedded SCR NMOS and low capacitance ESD protection device.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002


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