Jian Cao
Affiliations:- Peking University, School of Software and Microelectronics, Institute of Microelectronics, Beijing, China
According to our database1,
Jian Cao
authored at least 27 papers
between 2013 and 2024.
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Bibliography
2024
Proceedings of the IEEE International Conference on Acoustics, 2024
2023
An Efficient Neuromorphic Implementation of Temporal Coding-Based On-Chip STDP Learning.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023
Proceedings of the Thirty-Second International Joint Conference on Artificial Intelligence, 2023
Proceedings of the Neural Information Processing - 30th International Conference, 2023
Proceedings of the 25th International Conference on Advanced Communication Technology, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Unsupervised Learning of Spike-Timing-Dependent Plasticity Based on a Neuromorphic Implementation.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Proceedings of the 5th IEEE International Conference on Information Systems and Computer Aided Education, 2022
Proceedings of the 24th International Conference on Advanced Communication Technology, 2022
An Once-for-All Budgeted Pruning Framework for ConvNets Considering Input Resolution.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2022
Proceedings of the Computer Vision - ACCV 2022, 2022
2021
CoRR, 2021
2020
Proceedings of the AIAM2020: 2nd International Conference on Artificial Intelligence and Advanced Manufacture, 2020
2017
IEICE Electron. Express, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
IEICE Electron. Express, 2016
Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process.
Sci. China Inf. Sci., 2016
Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process.
Sci. China Inf. Sci., 2016
Sci. China Inf. Sci., 2016
A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling.
Sci. China Inf. Sci., 2015
Optimization design of a low power asynchronous DES for security applications based on Balsa and synchronous tools.
Proceedings of the 25. International Conference on Electronics, 2015
Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protection.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2013
Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits.
Proceedings of the IEEE 10th International Conference on ASIC, 2013