Jiajia Li

According to our database, Jiajia Li authored at least 24 papers between 2013 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution.

Kwangsoo Han, Andrew B. Kahng, Jiajia Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019

Enhancing sensitivity-based power reduction for an industry IC design context.

Hamed Fatemi, Andrew B. Kahng, Hyein Lee, Jiajia Li, José Pineda de Gyvez

Integr., 2019

2018

PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility.

Alex Kahng, Andrew B. Kahng, Hyein Lee, Jiajia Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes.

Sorin Dobre, Andrew B. Kahng, Jiajia Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality

Jiajia Li

PhD thesis, 2017

Logic Design Partitioning for Stacked Power Domains.

Kristof Blutman, Hamed Fatemi, Ajay Kapoor, Andrew B. Kahng, Jiajia Li, José Pineda de Gyvez

IEEE Trans. Very Large Scale Integr. Syst., 2017

Trading Accuracy for Energy in Stochastic Circuit Design.

Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li

ACM J. Emerg. Technol. Comput. Syst., 2017

Revisiting 3DIC benefit with multiple tiers.

Wei-Ting Jonas Chan, Andrew B. Kahng, Jiajia Li

Integr., 2017

Floorplan and placement methodology for improved energy reduction in stacked power-domain design.

Kristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li, José Pineda de Gyvez

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Improved flop tray-based design implementation for power reduction.

Andrew B. Kahng, Jiajia Li, Lutong Wang

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Measuring progress and value of IC implementation technology.

Andrew B. Kahng, Hyein Lee, Jiajia Li

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking.

Kwangsoo Han, Andrew B. Kahng, Jiajia Li

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Comprehensive optimization of scan chain timing during late-stage IC implementation.

Kun Young Chung, Andrew B. Kahng, Jiajia Li

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Optimization of Overdrive Signoff in High-Performance and Low-Power ICs.

Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath, Bongil Park

IEEE Trans. Very Large Scale Integr. Syst., 2015

An Improved Methodology for Resilient Design Implementation.

Andrew B. Kahng, Seokhyeong Kang, Jiajia Li, José Pineda de Gyvez

ACM Trans. Design Autom. Electr. Syst., 2015

Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes.

Sorin Dobre, Andrew B. Kahng, Jiajia Li

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs.

Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction.

Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementation.

Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Horizontal benchmark extension for improved assessment of physical CAD research.

Andrew B. Kahng, Hyein Lee, Jiajia Li

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A new methodology for reduced cost of resilience.

Andrew B. Kahng, Seokhyeong Kang, Jiajia Li

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013

Toward quantifying the IC design value of interconnect technology improvements.

Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

Reliability-constrained die stacking order in 3DICs under manufacturing variability.

Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li

Proceedings of the International Symposium on Quality Electronic Design, 2013

Optimization of overdrive signoff.

Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013