Jia Zhan

Orcid: 0000-0002-2179-4095

According to our database1, Jia Zhan authored at least 20 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
Design of Joint Source-Channel Coding Scheme Based on Spatially-Coupled DP-LDPC Codes.
IEEE Commun. Lett., April, 2024

2023
Joint Design of Source-Channel Codes With Linear Source Encoding Complexity and Good Channel Thresholds Based on Double-Protograph LDPC Codes.
IEEE Commun. Lett., November, 2023

2022
Design of Joint Source-Channel Codes Based on a Single Protograph.
CoRR, 2022

Implementation for JSCC Scheme Based on QC-LDPC Codes.
Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2021
Joint Source-Channel Codes Based on a Single Protograph.
Proceedings of the 11th International Symposium on Topics in Coding, 2021

2020
The independent indicators for differentiating renal cell carcinoma from renal angiomyolipoma by contrast-enhanced ultrasound.
BMC Medical Imaging, 2020

2018
Considerations on Multimodal Human-Computer Interaction.
Proceedings of the 5th IEEE International Conference on Cloud Computing and Intelligence Systems, 2018

2017
A Differential Chaotic Bit-Interleaved Coded Modulation System Over Multipath Rayleigh Channels.
IEEE Trans. Commun., 2017

2016
Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC.
IEEE Trans. Very Large Scale Integr. Syst., 2016

OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

A unified memory network architecture for in-memory computing in commodity servers.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Scalable memory fabric for silicon interposer-based multi-core systems.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
Exploring memory controller configurations for many-core systems with 3D stacked DRAMs.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

DimNoC: a dim silicon approach towards power-efficient on-chip network.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Core vs. uncore: the heart of darkness.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Designing vertical bandwidth reconfigurable 3D NoCs for many core systems.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Designing energy-efficient NoC for real-time embedded systems through slack optimization.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013


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