Jia Yu

According to our database, Jia Yu authored at least 10 papers between 2004 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Improving the throughput and delay performance of network processors by applying push model.

Bin Liu, Bo Yuan, Huichen Dai, Hongbo Zhao, Jia Yu, Laxmi N. Bhuyan

Proceedings of the 20th IEEE International Workshop on Quality of Service, 2012

2010

Experience on Applying Push Model to Packet Processors in High Performance Routers.

Bo Yuan, Hongbo Zhao, Chengchen Hu, Bin Liu, Jia Yu, Laxmi N. Bhuyan

Proceedings of the Global Communications Conference, 2010

2008

Revisiting the Cache Effect on Multicore Multithreaded Network Processors.

Zhen Liu, Jia Yu, Xiaojun Wang, Bin Liu, Laxmi N. Bhuyan

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

Conserving network processor power consumption by exploiting traffic variability.

Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan

ACM Trans. Archit. Code Optim., 2007

Program Mapping onto Network Processors by Recursive Bipartitioning and Refining.

Jia Yu, Jingnan Yao, Laxmi N. Bhuyan, Jun Yang

Proceedings of the 44th Design Automation Conference, 2007

2005

A low energy cache design for multimedia applications exploiting set access locality.

Jun Yang, Jia Yu, Youtao Zhang

J. Syst. Archit., 2005

Enhancing Network Processor Simulation Speed with Statistical Input Sampling.

Jia Yu, Jun Yang, Shaojie Chen, Yan Luo, Laxmi N. Bhuyan

Proceedings of the High Performance Embedded Architectures and Compilers, 2005

Assertion-Based Design Exploration of DVS in Network Processor Architectures.

Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin

Proceedings of the 2005 Design, 2005

Low power network processor design using clock gating.

Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan

Proceedings of the 42nd Design Automation Conference, 2005

2004

Assertion-based power/performance analysis of network processor architectures.

Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004