Jia Wang

Orcid: 0000-0002-6159-6085

Affiliations:

Illinois Institute of Technology, Department of Electrical and Computer Engineering, Chicago, IL, USA
Northwestern University, Electrical Engineering and Computer Science, Evanston, IL, USA (PhD 2008)

According to our database¹, Jia Wang authored at least 23 papers between 2004 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2024

Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., May, 2024

2023

GraphPlanner: Floorplanning with Graph Neural Network.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., March, 2023

2022

Floorplanning with graph attention.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2020

KNN-enhanced Deep Learning Against Noisy Labels.

[BibT_eX]

[DOI]

CoRR, 2020

2013

Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2010

Hybrid energy storage system integration for vehicles.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

iRetILP: an efficient incremental algorithm for min-period retiming under general delay model.

[BibT_eX]

[DOI]

Debasish Das

Jia Wang

Hai Zhou

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Gate Sizing by Lagrangian Relaxation Revisited.

[BibT_eX]

[DOI]

Jia Wang

Debasish Das

Hai Zhou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Risk aversion min-period retiming under process variations.

[BibT_eX]

[DOI]

Jia Wang

Hai Zhou

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Exploring adjacency in floorplanning.

[BibT_eX]

[DOI]

Jia Wang

Hai Zhou

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Linear constraint graph for floorplan optimization with soft blocks.

[BibT_eX]

[DOI]

Jia Wang

Hai Zhou

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

An efficient incremental algorithm for min-area retiming.

[BibT_eX]

[DOI]

Jia Wang

Hai Zhou

Proceedings of the 45th Design Automation Conference, 2008

2007

Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing.

[BibT_eX]

[DOI]

Jia Wang

Hai Zhou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Unified Incremental Physical-Level and High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Address generation for nanowire decoders.

[BibT_eX]

[DOI]

Jia Wang

Ming-Yang Kao

Hai Zhou

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

Clustering for Processing Rate Optimization.

[BibT_eX]

[DOI]

Chuan Lin

Jia Wang

Hai Zhou

IEEE Trans. Very Large Scale Integr. Syst., 2006

Processing Rate Optimization by Sequential System Floorplanning.

[BibT_eX]

[DOI]

Jia Wang

Hai Zhou

Ping-Chih Wu

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Optimal jumper insertion for antenna avoidance under ratio upper-bound.

[BibT_eX]

[DOI]

Jia Wang

Hai Zhou

Proceedings of the 43rd Design Automation Conference, 2006

TAPHS: thermal-aware unified physical-level and high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Incremental exploration of the combined physical and behavioral design space.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Interconnect estimation without packing via ACG floorplans.

[BibT_eX]

[DOI]

Jia Wang

Hai Zhou

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

ACG-Adjacent Constraint Graph for General Floorplans.

[BibT_eX]

[DOI]

Hai Zhou

Jia Wang

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Minimal period retiming under process variations.

[BibT_eX]

[DOI]

Jia Wang

Hai Zhou

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Jia Wang

Timeline

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