Jia Di

Orcid: 0000-0001-7718-0220

According to our database1, Jia Di authored at least 71 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Half-Xor: A Fully-Dynamic Sketch for Estimating the Number of Distinct Values in Big Tables.
IEEE Trans. Knowl. Data Eng., July, 2024

Seeing Is Believing: Extracting Semantic Information from Video for Verifying IoT Events.
Proceedings of the 17th ACM Conference on Security and Privacy in Wireless and Mobile Networks, 2024

TrustEvent: Cross-Platform IoT Trigger Event Verification Using Edge Computing.
Proceedings of the IEEE International Conference on Communications, 2024

Calibratable Polymorphic Temperature Sensor for Detecting Fault Injection and Side-Channel Attacks.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

Amnesiac Memory: A Self-Destructive Polymorphic Mechanism Against Cold Boot Data Remanence Attack.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2023
Case Study for Skewing MTNCL Circuits.
Proceedings of the 28th IEEE International Symposium on Asynchronous Circuits and Systems, 2023

An Internet of Things Testbed for Education and Community Research.
Proceedings of the IEEE International Conference on Artificial Intelligence, 2023

2022
Use It-No Need to Shake It!: Accurate Implicit Authentication for Everyday Objects with Smart Sensing.
Proc. ACM Interact. Mob. Wearable Ubiquitous Technol., 2022

Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism.
J. Electron. Test., 2022

Using dummy data for RFID tag and reader authentication.
Digit. Commun. Networks, 2022

2021
Building Fast and Compact Sketches for Approximately Multi-Set Multi-Membership Querying.
Proceedings of the SIGMOD '21: International Conference on Management of Data, 2021

Character Reassignment for Hardware Trojan Detection.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Rapid Configuration of Asynchronous Recurrent Neural Networks for ASIC Implementations.
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021

Design of Asynchronous Polymorphic Logic Gates for Hardware Security.
Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021

Reconfigurable ASIC Implementation of Asynchronous Recurrent Neural Networks.
Proceedings of the 27th IEEE International Symposium on Asynchronous Circuits and Systems, 2021

2020
Fork Path: Batching ORAM Requests to Remove Redundant Memory Accesses.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Reducing Power Consumption in Asynchronous MTNCL Circuits through Selective Sleep.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates.
Proceedings of the IEEE International Test Conference, 2020

Wireless Sensor Node Platform for In-Plant Stress Monitoring.
Proceedings of the 2020 IEEE Sensors, Rotterdam, The Netherlands, October 25-28, 2020, 2020

2019
Hardware IP Classification through Weighted Characteristics.
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

2018
Clockless Spintronic Logic: A Robust and Ultra-Low Power Computing Paradigm.
IEEE Trans. Computers, 2018

The Old Frontier of Reverse Engineering: Netlist Partitioning.
J. Hardw. Syst. Secur., 2018

Comprehensive Comparison of NULL Convention Logic Threshold Gate Implementations.
Proceedings of the 2018 New Generation of CAS, 2018

Hardware Trojan Detection and Functionality Determination for Soft IPs.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

2017
Obfuscation-Based Protection Framework against Printed Circuit Boards Unauthorized Operation and Reverse Engineering.
ACM Trans. Design Autom. Electr. Syst., 2017

A SiC CMOS Digitally Controlled PWM Generator for High-Temperature Applications.
IEEE Trans. Ind. Electron., 2017

Recent Advances in Low Power Asynchronous Circuit Design.
J. Low Power Electron., 2017

Golden reference matching for gate-level netlist functionality identification.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016
Multi-threshold dual-spacer dual-rail delay-insensitive logic: An improved IC design methodology for side channel attack mitigation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Tracking Data Flow at Gate-Level through Structural Checking.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

A novel PUF based on cell error rate distribution of STT-RAM.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Evaluating the capability and performance of access control policy verification tools.
Proceedings of the 34th IEEE Military Communications Conference, 2015

Fork path: improving efficiency of ORAM by removing redundant memory accesses.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

The effects of flooding attacks on time-critical communications in the smart grid.
Proceedings of the 2015 IEEE Power & Energy Society Innovative Smart Grid Technologies Conference, 2015

Chip-level anti-reverse engineering using transformable interconnects.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Investigation of obfuscation-based anti-reverse engineering for printed circuit boards.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Teaching RFID Information Systems Security.
IEEE Trans. Educ., 2014

Asynchronous Parallel Platforms with Balanced Performance and Energy.
J. Low Power Electron., 2014

Exploiting hidden Markov models in identifying passive UHF RFID tags.
Proceedings of the 2014 IEEE Radio and Wireless Symposium, 2014

Framework of a scalable delay-insensitive asynchronous platform enabling heterogeneous concurrency.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

An asynchronous finite impulse response filter design for Digital Signal Processing circuit.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Framework of an Adaptive Delay-Insensitive Asynchronous Platform for Energy Efficiency.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A comparative analysis of 3D-IC partitioning schemes for asynchronous circuits.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

2013
Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic.
Microelectron. J., 2013

An Asynchronous Advanced Encryption Standard Core Design for Energy Efficiency.
J. Low Power Electron., 2013

An efficient run-time encryption scheme for non-volatile main memory.
Proceedings of the International Conference on Compilers, 2013

2012
Feature selection for RFID tag identification.
Proceedings of the 7th International Conference on Communications and Networking in China, 2012

2011
Fingerprinting RFID Tags.
IEEE Trans. Dependable Secur. Comput., 2011

A 12-bit CMOS current steering D/A converter with a fully differential voltage output.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

A new topology for fully differential amplifiers that enhances their tolerance to external disturbances.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Integrating Asynchronous Digital Design Into the Computer Engineering Curriculum.
IEEE Trans. Educ., 2010

Analysis and Improvement of Delay-Insensitive Asynchronous Circuits Operating in Subthreshold Regime.
J. Low Power Electron., 2010

Delay-Insensitive Cell Matrix.
Proceedings of the 2010 International Conference on Computer Design, 2010

2009
Designing Asynchronous Circuits using NULL Convention Logic (NCL)
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79800-9, 2009

Glitch-free design for multi-threshold CMOS NCL circuits.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Delay-Insensitive Ternary Logic.
Proceedings of the 2009 International Conference on Computer Design, 2009

Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power.
J. Low Power Electron., 2008

Ownership Transfer of RFID Tags based on Electronic Fingerprint.
Proceedings of the 2008 International Conference on Security & Management, 2008

2007
Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems.
J. Electron. Test., 2007

2006
Reversible-logic design with online testability.
IEEE Trans. Instrum. Meas., 2006

Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design.
J. Low Power Electron., 2006

Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design.
Integr., 2006

Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2005
Teaching low-power electronic design in electrical and computer engineering.
IEEE Trans. Educ., 2005

D3L - A framework on fighting against non-invasive attacks to integrated circuits for security applications.
Proceedings of the Third IASTED International Conference on Circuits, 2005

On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers.
Proceedings of the 2005 International Conference on Computer Design, 2005

2003
High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Power-aware pipelined multiplier design based on 2-dimensional pipeline gating.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003


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