Ji-Yong Um

Orcid: 0000-0002-0180-0400

According to our database1, Ji-Yong Um authored at least 13 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Arterial Distension Monitoring Scheme Using FPGA-Based Inference Machine in Ultrasound Scanner Circuit System.
IEEE Trans. Biomed. Circuits Syst., June, 2024

2023
Center Frequency Tracking Scheme to Optimize Pulse-Echo Response of Ultrasonic A-mode Scanner Circuit System.
IEEE Access, 2023

Design and implementation of autonomous collaboration service between IoT using distributed platform.
Proceedings of the Fourteenth International Conference on Ubiquitous and Future Networks, 2023

2022
A Compact Variable Gain Amplifier With Continuous Time-Gain Compensation Using Systematic Predistorted Gain Control.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Programmable Gain Amplifier with Fast Transient Response for Medical Ultrasound System.
Proceedings of the 19th International SoC Design Conference, 2022

2017
A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation.
IEEE Trans. Biomed. Circuits Syst., 2017

2015
A Single-Chip 32-Channel Analog Beamformer With 4-ns Delay Resolution and 768-ns Maximum Delay Range for Ultrasound Medical Imaging With a Linear Array Transducer.
IEEE Trans. Biomed. Circuits Syst., 2015

Power noise rejection and device noise analysis at the reference level of ramp ADC.
Proceedings of the Image Sensors and Imaging Systems 2015, 2015

2014
An Analog-Digital Hybrid RX Beamformer Chip With Non-Uniform Sampling for Ultrasound Medical Imaging With 2D CMUT Array.
IEEE Trans. Biomed. Circuits Syst., 2014

24.8 An analog-digital-hybrid single-chip RX beamformer with non-uniform sampling for 2D-CMUT ultrasound imaging to achieve wide dynamic range of delay and small chip area.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2011
Time-interleaved sample clock generator for ultrasound beamformer application.
Proceedings of the International SoC Design Conference, 2011

Digital-domain calibration of split-capacitor DAC with no extra calibration DAC for a differential-type SAR ADC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011


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