Ji-Hoon Lim
According to our database1,
Ji-Hoon Lim
authored at least 13 papers
between 2007 and 2023.
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Bibliography
2023
Differential Power Processing Converter With Active Clamp Structure and Integrated Planar Transformer for Power Generation Optimization of Multiple Photovoltaic Submodules.
IEEE Access, 2023
Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023
Inductor Design of Interleaved Totem-Pole Bridgeless Boost PFC Based on Pareto Optimization.
Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023
2016
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits, 2016
2013
A Digitally-Controlled SMPS Using a Novel High-Resolution DPWM Generator Based on a Pseudo Relaxation-Oscillation Technique.
IEICE Trans. Electron., 2013
2012
One-chip multi-output SMPS using a shared digital controller and a pseudo relaxation oscillating technique.
Proceedings of the International SoC Design Conference, 2012
2011
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction.
IEEE J. Solid State Circuits, 2011
J. Circuits Syst. Comput., 2011
2010
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2008
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.
IEEE J. Solid State Circuits, 2008
2007
A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips.
IEICE Trans. Electron., 2007
An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007