Ji-Hak Yu

According to our database¹, Ji-Hak Yu authored at least 4 papers between 2015 and 2019.

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2019

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

2018

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2016

A 2ps minimum-resolution, wide-input-range time-to-digital converter for the time-of-flight measurement using cyclic technique and time amplifier.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2016

2015

An inverter layout technique for propagation delay minimization.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Consumer Electronics, 2015