Ji Gu

Orcid: 0000-0002-4831-3706

According to our database1, Ji Gu authored at least 16 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
RIS-Assisted Multi-Carrier Secret Key Generation in Static Environments.
IEEE Wirel. Commun. Lett., October, 2024

SharpEdge: A QoS-driven task scheduling scheme with blockchain in mobile edge computing.
Concurr. Comput. Pract. Exp., August, 2024

2023
Computer vision aided beamforming for indoor scenario at sub-6GHz.
Dataset, October, 2023

Reputation-Aware Supplier Assessment for Blockchain-Enabled Supply Chain in Industry 4.0.
IEEE Trans. Ind. Informatics, April, 2023

2013
DLIC: Decoded loop instructions caching for energy-aware embedded processors.
ACM Trans. Embed. Comput. Syst., 2013

2012
A Case Study of Energy-efficient Loop Instruction Cache Design for Embedded Multitasking Systems.
Proceedings of the SMARTGREENS 2012 - Proceedings of the 1st International Conference on Smart Grids and Green IT Systems, Porto, Portugal, 19, 2012

Loop instruction caching for energy-efficient embedded multitasking processors.
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

2011
Application-specific design of low power instruction cache hierarchy for embedded processors.
PhD thesis, 2011

An on-chip instruction cache design with one-bit tag for low-power embedded systems.
Microprocess. Microsystems, 2011

Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems.
Int. J. Handheld Comput. Res., 2011

2010
An Energy Efficient Instruction Prefetching Scheme for Embedded Processors.
Proceedings of the Ubiquitous Computing and Multimedia Applications, 2010

Enabling large decoded instruction loop caching for energy-aware embedded processors.
Proceedings of the 2010 International Conference on Compilers, 2010

2009
An Efficient Segmental Bus-Invert Coding Method for Instruction Memory Data Bus Switching Reduction.
EURASIP J. Embed. Syst., 2009

ROBTIC: An On-chip Instruction Cache Design for Low Power Embedded Systems.
Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009

A Segmental Bus-invert Coding Method for Instruction Memory Data Bus Power Efficiency.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Upscaling methods for a class of convection-diffusion equations with highly oscillating coefficients.
J. Comput. Phys., 2008


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