Jhon-Jhy Liaw

According to our database, Jhon-Jhy Liaw authored at least 8 papers between 2014 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications.

Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications.

Jonathan Chang, Yen-Huei Chen, Gary Chan, Kuo-Cheng Lin, Po-Sheng Wang, Yangsyu Lin, Sevic Chen, Peijiun Lin, Ching-Wei Wu, Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Atul Katoch, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2019

A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue.

Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Cheng-Han Lin, Po-Yi Huang, Kao-Cheng Lin, Jhon-Jhy Liaw, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2017

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.

Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Sahil Preet Singh, Hank Cheng, Hidehiro Fujiwara, Jih-Yu Lin, Kao-Cheng Lin, John Hung, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications.

Yen-Huei Chen, Kao-Cheng Lin, Ching-Wei Wu, Wei-Min Chan, Jhon-Jhy Liaw, Hung-Jen Liao, Jonathan Chang

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015

A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications.

Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Jonathan Chang

IEEE J. Solid State Circuits, 2015

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies.

Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Kao-Cheng Lin, Dar Sun, Shin-Rung Wu, Jhon-Jhy Liaw, Chih-Yung Lin, Mu-Chi Chiang, Hung-Jen Liao, Shien-Yang Wu, Jonathan Chang

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.

Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, George H. Chang, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Sreedhar Natarajan, Jonathan Chang

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014