Jhih-Ying Ke

According to our database, Jhih-Ying Ke authored at least 4 papers between 2023 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm.

Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Jhih-Ying Ke, Cheng-Yao Lo, Tzung-Je Lee, Lean Karlo Santos Tolentino

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024

A 266.7 TOPS/W Computing-in Memory Using Single-Ended 6T 4-kb SRAM in 16-nm FinFET CMOS Process.

Cheng-Yao Lo, Lean Karlo Santos Tolentino, Jhih-Ying Ke, Jeffrey S. Walling, Yang Yi, Chua-Chin Wang

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process.

Jhih-Ying Ke, Lean Karlo Santos Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process.

Jhih-Ying Ke, Lean Karlo S. Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023