Jhih-Rong Gao

According to our database, Jhih-Rong Gao authored at least 25 papers between 2007 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization.

Yuzhe Ma, Wei Zhong, Shuxiang Hu, Jhih-Rong Gao, Jian Kuang, Jin Miao, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2018

MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes.

Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

A unified framework for simultaneous layout decomposition and mask optimization.

Yuzhe Ma, Jhih-Rong Gao, Jian Kuang, Jin Miao, Bei Yu

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

EBL Overlapping Aware Stencil Planning for MCC System.

Bei Yu, Kun Yuan, Jhih-Rong Gao, Shiyan Hu, David Z. Pan

ACM Trans. Design Autom. Electr. Syst., 2016

PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning.

Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan

ACM Trans. Design Autom. Electr. Syst., 2016

2015

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography.

Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles J. Alpert, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design.

Jiaojiao Ou, Bei Yu, Jhih-Rong Gao, David Z. Pan, Moshe Preil, Azat Latypov

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session).

Bei Yu, Subhendu Roy, Jhih-Rong Gao, David Z. Pan

CoRR, 2014

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting.

Bei Yu, Jhih-Rong Gao, David Z. Pan

CoRR, 2014

Lithography Hotspot Detection and Mitigation in Nanometer VLSI.

Jhih-Rong Gao, Bei Yu, David Z. Pan

CoRR, 2014

Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement.

Jhih-Rong Gao, Bei Yu, Ru Huang, David Z. Pan

CoRR, 2014

MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction.

Jhih-Rong Gao, Xiaoqing Xu, Bei Yu, David Z. Pan

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Self-aligned double patterning layout decomposition with complementary e-beam lithography.

Jhih-Rong Gao, Bei Yu, David Z. Pan

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Design for Manufacturing With Emerging Nanolithography.

David Z. Pan, Bei Yu, Jhih-Rong Gao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Methodology for standard cell compliance and detailed placement for triple patterning lithography.

Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, David Z. Pan

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system.

Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

L-shape based layout fracturing for e-beam lithography.

Bei Yu, Jhih-Rong Gao, David Z. Pan

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Lithography hotspot detection and mitigation in nanometer VLSI.

Jhih-Rong Gao, Bei Yu, Duo Ding, David Z. Pan

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

VLSI CAD for emerging nanolithography.

David Z. Pan, Jhih-Rong Gao, Bei Yu

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Flexible self-aligned double patterning aware detailed routing with prescribed layout planning.

Jhih-Rong Gao, David Z. Pan

Proceedings of the International Symposium on Physical Design, 2012

Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper).

Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection.

Duo Ding, Jhih-Rong Gao, Kun Yuan, David Z. Pan

Proceedings of the 48th Design Automation Conference, 2011

2010

NTHU-Route 2.0: A Robust Global Router for Modern Designs.

Yen-Jung Chang, Yu-Ting Lee, Jhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2008

A new global router for modern designs.

Jhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction.

Pei-Ci Wu, Jhih-Rong Gao, Ting-Chi Wang

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007