Jesús Urresti-Ibañez

Orcid: 0000-0002-0442-4551

According to our database1, Jesús Urresti-Ibañez authored at least 9 papers between 2003 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2014
Overload robust IGBT design for SSCB application.
Microelectron. Reliab., 2014

3.3 kV PT-IGBT with voltage-sensor monolithically integrated.
IET Circuits Devices Syst., 2014

2012
Study of layout influence on ruggedness of NPT-IGBT devices by physical modelling.
Microelectron. Reliab., 2012

2011
Analysis of Clamped Inductive Turnoff Failure in Railway Traction IGBT Power Modules Under Overload Conditions.
IEEE Trans. Ind. Electron., 2011

2008
IGBT module failure analysis in railway applications.
Microelectron. Reliab., 2008

2007
Robustness test and failure analysis of IGBT modules during turn-off.
Microelectron. Reliab., 2007

2005
Lateral punch-through TVS devices for on-chip protection in low-voltage applications.
Microelectron. Reliab., 2005

Analysis of hot-carrier degradation in a SOI LDMOS transistor with a steep retrograde drift doping profile.
Microelectron. Reliab., 2005

2003
Optimisation of very low voltage TVS protection devices.
Microelectron. J., 2003


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