Jesús Camacho Villanueva

According to our database, Jesús Camacho Villanueva authored at least 6 papers between 2009 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems.

Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

PC-Mesh: A Dynamic Parallel Concentrated Mesh.

Jesús Camacho Villanueva, José Flich, Antoni Roca, José Duato

Proceedings of the International Conference on Parallel Processing, 2011

Towards an Efficient NoC Topology through Multiple Injection Ports.

Jesús Camacho Villanueva, José Flich, José Duato, Hans Eberle, Wladek Olesinski

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

HPC-Mesh: A Homogeneous Parallel Concentrated Mesh for Fault-Tolerance and Energy Savings.

Jesús Camacho Villanueva, José Flich

Proceedings of the 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2011

2010

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing.

Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato

Proceedings of the NOCS 2010, 2010

2009

A performance evaluation of 2D-mesh, ring, and crossbar interconnects for chip multi-processors.

Jesús Camacho Villanueva, José Flich, José Duato, Hans Eberle, Nils Gura, Wladek Olesinski

Proceedings of the Second International Workshop on Network on Chip Architectures, 2009