Jestoni V. Zarsuela

According to our database, Jestoni V. Zarsuela authored at least 2 papers between 2008 and 2010.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2010

A Simulation of Cache Sub-banking and Block Buffering as Power Reduction Techniques for Multiprocessor Cache Design.

Jestoni V. Zarsuela, Anastacia B. Alvarez, Joy Alinda Reyes

Proceedings of the 12th UKSim, 2010

2008

DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache.

Darryl Aldrin M. Dioquino, Katrina Joy S. Rosario, Homer F. Supe, Jestoni V. Zarsuela, Anastacia P. Ballesil, Joy Alinda Reyes

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008