Jerome Quartana

According to our database, Jerome Quartana authored at least 6 papers between 2001 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

Integrated Evaluation Platform for Secured Devices.

Pascal Manet, Jean-Baptiste Rigaud, Julien Francq, Marc Jeambrun, Assia Tria, Bruno Robisson, Jerome Quartana, Selma Laabidi

Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

2005

Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping.

Jerome Quartana, Laurent Fesquet, Marc Renaudin

Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Asynchronous Systems on Programmable Logic.

Laurent Fesquet, Jerome Quartana, Marc Renaudin

Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips.

Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2002

High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems.

Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana

Proceedings of the 2002 Design, 2002

2001

Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems.

Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin

Proceedings of the SOC Design Methodologies, 2001