Jérôme Ermont
Orcid: 0000-0002-9972-9621
According to our database1,
Jérôme Ermont
authored at least 29 papers
between 2002 and 2024.
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Bibliography
2024
Invited Paper: Assessing Unchecked Factors for Certification: An Experimental Approach for GPU Cache Parameters.
Proceedings of the 22nd International Workshop on Worst-Case Execution Time Analysis, 2024
Proceedings of the 30th IEEE Real-Time and Embedded Technology and Applications Symposium, 2024
2022
Proceedings of the 18th IEEE International Conference on Factory Communication Systems, 2022
2020
Proceedings of the 18th IEEE International Conference on Industrial Informatics, 2020
Impact of frame size and deadlines on WRR scheduling in a switched Ethernet network with critical and non-critical flows.
Proceedings of the 25th IEEE International Conference on Emerging Technologies and Factory Automation, 2020
2019
Proceedings of the 27th International Conference on Real-Time Networks and Systems, 2019
Limiting over sampling to improve transmission schedulability in a mixed NoC/AFDX architecture.
Proceedings of the 24th IEEE International Conference on Emerging Technologies and Factory Automation, 2019
2018
Proceedings of the 14th IEEE International Workshop on Factory Communication Systems, 2018
Proceedings of the 26th International Conference on Real-Time Networks and Systems, 2018
2017
Extended recursive analysis for tilera tile64 NoC architectures: towards inter-NoC delay analysis.
SIGBED Rev., 2017
Proceedings of the IEEE 13th International Workshop on Factory Communication Systems, 2017
2016
Towards a unified approach for worst-case analysis of Tilera-like and KalRay-like NoC architectures.
Proceedings of the IEEE World Conference on Factory Communication Systems, 2016
Poster Abstract: I/O Contention Aware Mapping of Multi-Criticalities Real-Time Applications over Many-Core Architectures.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016
Reducing the Contention Experienced by Real-Time Core-to-I/O Flows over a Tilera-Like Network on Chip.
Proceedings of the 28th Euromicro Conference on Real-Time Systems, 2016
2015
Wormhole networks properties and their use for optimizing worst case delay analysis of many-cores.
Proceedings of the 10th IEEE International Symposium on Industrial Embedded Systems, 2015
2014
Int. J. Crit. Comput. Based Syst., 2014
2013
Freshness and Reactivity Analysis in Globally Asynchronous Locally Time-Triggered Systems.
Proceedings of the NASA Formal Methods, 2013
Modeling a spacewire architecture using timed automata to compute worst-case end-to-end delays.
Proceedings of 2013 IEEE 18th Conference on Emerging Technologies & Factory Automation, 2013
2012
An improved timed automata approach for computing exact worst-case delays of AFDX sporadic flows.
Proceedings of 2012 IEEE 17th International Conference on Emerging Technologies & Factory Automation, 2012
2011
Proceedings of the 13th IEEE International Symposium on High-Assurance Systems Engineering, 2011
Proceedings of the IEEE 16th Conference on Emerging Technologies & Factory Automation, 2011
2010
Proceedings of the Leveraging Applications of Formal Methods, Verification, and Validation, 2010
Proceedings of 15th IEEE International Conference on Emerging Technologies and Factory Automation, 2010
2009
Innov. Syst. Softw. Eng., 2009
2007
Proceedings of the ISoLA 2007, 2007
2006
Proceedings of the 18th Euromicro Conference on Real-Time Systems, 2006
2005
Proceedings of 10th IEEE International Conference on Emerging Technologies and Factory Automation, 2005
2003
Tech. Sci. Informatiques, 2003
2002
TPAP: an Algebra of Preemptive Processes for Verifying Real-Time Systems with Shared Resources.
Proceedings of the Theory and Practice of Timed Systems, 2002