Jérôme Ermont

Orcid: 0000-0002-9972-9621

According to our database1, Jérôme Ermont authored at least 29 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Invited Paper: Assessing Unchecked Factors for Certification: An Experimental Approach for GPU Cache Parameters.
Proceedings of the 22nd International Workshop on Worst-Case Execution Time Analysis, 2024

A Hybrid Approach to WCTT Analysis in a Real-Time Switched Ethernet Network.
Proceedings of the 30th IEEE Real-Time and Embedded Technology and Applications Symposium, 2024

2022
An evaluation of software-based TSN traffic shapers using Linux tc.
Proceedings of the 18th IEEE International Conference on Factory Communication Systems, 2022

2020
Efficient configuration of a QoS-aware AFDX network with Deficit Round Robin.
Proceedings of the 18th IEEE International Conference on Industrial Informatics, 2020

Impact of frame size and deadlines on WRR scheduling in a switched Ethernet network with critical and non-critical flows.
Proceedings of the 25th IEEE International Conference on Emerging Technologies and Factory Automation, 2020

2019
Quantum assignment for QoS-aware AFDX network with deficit round robin.
Proceedings of the 27th International Conference on Real-Time Networks and Systems, 2019

Limiting over sampling to improve transmission schedulability in a mixed NoC/AFDX architecture.
Proceedings of the 24th IEEE International Conference on Emerging Technologies and Factory Automation, 2019

2018
Reducing AFDX jitter in a mixed NoC/AFDX architecture.
Proceedings of the 14th IEEE International Workshop on Factory Communication Systems, 2018

Message scheduling to reduce AFDX jitter in a mixed NoC/AFDX architecture.
Proceedings of the 26th International Conference on Real-Time Networks and Systems, 2018

2017
Extended recursive analysis for tilera tile64 NoC architectures: towards inter-NoC delay analysis.
SIGBED Rev., 2017

Towards a mixed NoC/AFDX architecture for avionics applications.
Proceedings of the IEEE 13th International Workshop on Factory Communication Systems, 2017

2016
Towards a unified approach for worst-case analysis of Tilera-like and KalRay-like NoC architectures.
Proceedings of the IEEE World Conference on Factory Communication Systems, 2016

Poster Abstract: I/O Contention Aware Mapping of Multi-Criticalities Real-Time Applications over Many-Core Architectures.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

Reducing the Contention Experienced by Real-Time Core-to-I/O Flows over a Tilera-Like Network on Chip.
Proceedings of the 28th Euromicro Conference on Real-Time Systems, 2016

2015
Wormhole networks properties and their use for optimizing worst case delay analysis of many-cores.
Proceedings of the 10th IEEE International Symposium on Industrial Embedded Systems, 2015

2014
End-to-end latency and temporal consistency analysis in networked real-time systems.
Int. J. Crit. Comput. Based Syst., 2014

2013
Freshness and Reactivity Analysis in Globally Asynchronous Locally Time-Triggered Systems.
Proceedings of the NASA Formal Methods, 2013

Modeling a spacewire architecture using timed automata to compute worst-case end-to-end delays.
Proceedings of 2013 IEEE 18th Conference on Emerging Technologies & Factory Automation, 2013

2012
An improved timed automata approach for computing exact worst-case delays of AFDX sporadic flows.
Proceedings of 2012 IEEE 17th International Conference on Emerging Technologies & Factory Automation, 2012

2011
Worst Case Temporal Consistency in Integrated Modular Avionics Systems.
Proceedings of the 13th IEEE International Symposium on High-Assurance Systems Engineering, 2011

Latency and freshness analysis on IMA systems.
Proceedings of the IEEE 16th Conference on Emerging Technologies & Factory Automation, 2011

2010
Analyzing End-to-End Functional Delays on an IMA Platform.
Proceedings of the Leveraging Applications of Formal Methods, Verification, and Validation, 2010

Model for worst case delay analysis of an AFDX network using timed automata.
Proceedings of 15th IEEE International Conference on Emerging Technologies and Factory Automation, 2010

2009
Verification of real-time systems with preemption: negative and positive results.
Innov. Syst. Softw. Eng., 2009

2007
Verification of embbeded systems with preemption: a negative result.
Proceedings of the ISoLA 2007, 2007

2006
Methods for bounding end-to-end delays on an AFDX network.
Proceedings of the 18th Euromicro Conference on Real-Time Systems, 2006

2005
TTCAN over mixed CAN/switched Ethernet architecture.
Proceedings of 10th IEEE International Conference on Emerging Technologies and Factory Automation, 2005

2003
Trois approches pour la modélisation et la vérification de systèmes embarqués.
Tech. Sci. Informatiques, 2003

2002
TPAP: an Algebra of Preemptive Processes for Verifying Real-Time Systems with Shared Resources.
Proceedings of the Theory and Practice of Timed Systems, 2002


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