Jeremy Holleman

Affiliations:
  • University of Tennessee, Knoxville, USA


According to our database1, Jeremy Holleman authored at least 44 papers between 1997 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Fast Simulation of Analog Spiking Neural Network With Device Non-Idealites.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

A 1mW Always-on Computer Vision Deep Learning Neural Decision Processor.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2021
MLPerf Tiny Benchmark.
CoRR, 2021

Training Neural Networks Using the Property of Negative Feedback to Inverse a Function.
CoRR, 2021


Hardware Model Based Simulation of Spiking Neuron Using Phase Plane.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Benchmarking TinyML Systems: Challenges and Direction.
CoRR, 2020

Spiking Sparse Coding Algorithm with Reduced Inhibitory Feedback Weights.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Leakage Current Compensation in Large Number of Inactive Synapses in a 130nm CMOS Process.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Low Power Compact Analog Spiking Neuron Circuit Using Exponential Positive Feedback With Adaptation and Bursting Capability.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2018
A Digitally Interfaced Analog Correlation Filter System for Object Tracking Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Implementation of Linear Discriminant Classifier in 130nm Silicon Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Sub-1V-Read Flash Memory in a Standard 130nm CMOS Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A fast convergent and energy efficient offset calibration technique for dynamic comparators.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Deep modeling: Circuit characterization using theory based models in a data driven framework.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
The impact of analog computational error on an analog boolean satisfiability solver.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Design considerations for neural amplifiers.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

2015
An Ultralow-Power Low-Noise CMOS Biopotential Amplifier for Neural Recording.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 1 TOPS/W Analog Deep Machine-Learning Engine With Floating-Gate Storage in 0.13 µm CMOS.
IEEE J. Solid State Circuits, 2015

A 167 μW 915 MHz gain-boosted LC VCO.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A configurable 5.9 μW analog front-end for biosignal acquisition.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Analog inference circuits for deep learning.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
On the Impact of Approximate Computation in an Analog DeSTIN Architecture.
IEEE Trans. Neural Networks Learn. Syst., 2014

A current-reuse complementary-input chopper-stabilized amplifier for neural recording.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

A low-power 84-dB dynamic-range tunable Gm-C filter for bio-signal acquisition.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

30.10 A 1TOPS/W analog deep machine-learning engine with floating-gate storage in 0.13μm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A Low-Power High-Precision Comparator With Time-Domain Bulk-Tuned Offset Cancellation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A high input impedance low-noise instrumentaion amplifier with JFET input.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A floating-gate analog memory with bidirectional sigmoid updates in a standard digital process.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Design of Ultra-Low Power Biopotential Amplifiers for Biosignal Acquisition Applications.
IEEE Trans. Biomed. Circuits Syst., 2012

An ultra-low voltage self-startup charge pump for energy harvesting applications.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

An ultra-low-power 902-928MHz RF receiver front-end in CMOS 90nm process.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A low-power dynamic comparator with time-domain bulk-driven offset cancellation.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A 3.3 µW dual-modulus frequency divider with 189% locking range for MICS band applications.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A wideband ultra-low-current on-chip ammeter.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2009
NeuralWISP: A Wirelessly Powered Neural Interface With 1-m Range.
IEEE Trans. Biomed. Circuits Syst., 2009

A 500µW neural tag with 2µVrms AFE and frequency-multiplying MICS/ISM FSK transmitter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Design Techniques for Self-powered Microsystems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations.
IEEE J. Solid State Circuits, 2008

A 3 µW CMOS True Random Number Generator With Adaptive Floating-Gate Offset Cancellation.
IEEE J. Solid State Circuits, 2008

A micro-power neural spike detector and feature extractor in .13μm CMOS.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A 1.6pJ/bit 96% Stable Chip-ID Generating Circuit using Process Variations.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A compact pulse-based charge pump in 0.13 μm CMOS.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

1997
Analog VLSI Model of Intersegmental Coordination with Nearest-Neighbor Coupling.
Proceedings of the Advances in Neural Information Processing Systems 10, 1997


  Loading...