Jeremie S. Kim
Orcid: 0000-0001-6153-9008
According to our database1,
Jeremie S. Kim
authored at least 59 papers
between 2014 and 2024.
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Bibliography
2024
ApHMM: Accelerating Profile Hidden Markov Models for Fast and Energy-efficient Genome Analysis.
ACM Trans. Archit. Code Optim., March, 2024
SpyHammer: Understanding and Exploiting RowHammer Under Fine-Grained Temperature Variations.
IEEE Access, 2024
2022
Dataset, July, 2022
RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory.
CoRR, 2022
COVIDHunter: COVID-19 pandemic wave prediction and mitigation via seasonality-aware modeling.
CoRR, 2022
GenStore: A High-Performance and Energy-Efficient In-Storage Computing System for Genome Sequence Analysis.
CoRR, 2022
Bioinform., 2022
AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
GenStore: In-Storage Filtering of Genomic Data for High-Performance and Energy-Efficient Genome Analysis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
SeGraM: a universal hardware accelerator for genomic sequence-to-graph and sequence-to-sequence mapping.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices.
Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022
GenStore: a high-performance in-storage processing system for genome sequence analysis.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022
2021
A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses.
CoRR, 2021
Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins.
CoRR, 2021
CoRR, 2021
pLUTo: In-DRAM Lookup Tables to Enable Massively Parallel General-Purpose Computation.
CoRR, 2021
BurstLink: Techniques for Energy-Efficient Conventional and Virtual Reality Video Display.
CoRR, 2021
COVIDHunter: An Accurate, Flexible, and Environment-Aware Open-Source COVID-19 Outbreak Simulation Model.
CoRR, 2021
Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
BurstLink: Techniques for Energy-Efficient Video Display for Conventional and Virtual Reality Systems.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chipsand Implications on Future Attacks and Defenses.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
IChannels: Exploiting Current Management Mechanisms to Create Covert Channels in Modern Processors.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
2020
Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins.
PhD thesis, 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Apollo: a sequencing-technology-independent, scalable and accurate assembly polishing algorithm.
Bioinform., 2020
Proceedings of the 2020 IEEE Symposium on Security and Privacy, 2020
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
2019
AirLift: A Fast and Comprehensive Technique for Remapping Alignments between Reference Genomes.
CoRR, 2019
CoRR, 2019
Nanopore sequencing technology and tools for genome assembly: computational analysis of the current state, bottlenecks and future directions.
Briefings Bioinform., 2019
CROW: a low-cost substrate for improving DRAM performance, energy efficiency, and reliability.
Proceedings of the 46th International Symposium on Computer Architecture, 2019
D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019
2018
D-RaNGe: Violating DRAM Timing Constraints for High-Throughput True Random Number Generation using Commodity DRAM Devices.
CoRR, 2018
GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies.
BMC Genom., 2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
2017
Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
2016
Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM.
CoRR, 2016
2014
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014