Jer-Min Jou

Proceedings of the Intelligent Systems and Applications, 2014

A Transaction-based Design Model and Its MPEG-2 Encoder Design.

[BibT_eX]

[DOI]

Chun-Yu Chen

Proceedings of the Intelligent Systems and Applications, 2014

2011

Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis.

[BibT_eX]

[DOI]

Sih-Sian Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010

An Optimal Round-Robin Arbiter Design for NoC.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2010

Efficient design and generation of a multi-facet arbiter.

[BibT_eX]

[DOI]

Sih-Sian Wu

Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

A high-speed and decentralized arbiter design for NoC.

[BibT_eX]

[DOI]

Yen-Yu Chen

Proceedings of the 7th IEEE/ACS International Conference on Computer Systems and Applications, 2009

2007

A Novel Reconfigurable Computation Unit for DSP Applications.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2005

A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC).

[BibT_eX]

[DOI]

Yuan-Long Jeang

Win-Hsien Huang

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

2004

Efficient Architectures for the Biorthogonal Wavelet Transform by Filter Bank and Lifting Scheme.

[BibT_eX]

[DOI]

Chin-Chi Liu

IEICE Trans. Inf. Syst., 2004

2002

Design of a dynamic pipelined architecture for fuzzy color correction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

2001

An efficient blocking-matching algorithm based on fuzzy reasoning.

[BibT_eX]

[DOI]

IEEE Trans. Syst. Man Cybern. Part B, 2001

Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme.

[BibT_eX]

[DOI]

Chin-Chi Liu

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

An efficient VLSI architecture for HMM-based speech recognition.

[BibT_eX]

[DOI]

Chen-Jen Huang

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

An adaptive fuzzy logic controller: its VLSI architecture and applications.

[BibT_eX]

[DOI]

Sheng-Fu Yang

IEEE Trans. Very Large Scale Integr. Syst., 2000

Adaptive arithmetic coding using fuzzy reasoning and grey prediction.

[BibT_eX]

[DOI]

Fuzzy Sets Syst., 2000

1999

The gray prediction search algorithm for block motion estimation.

[BibT_eX]

[DOI]

Jian-Ming Sun

IEEE Trans. Circuits Syst. Video Technol., 1999

A fast and efficient lossless data-compression method.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 1999

A grey prediction motion estimator for digital image processing.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

An efficient method for the decomposition and resynthesis of speed-independent circuits.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

A New Pipelined Architecture for Fuzzy Color Correction.

[BibT_eX]

[DOI]

Shiann-Rong Kuang

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Hazard-Free Synthesis and Decomposition of Asynchronous Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1997

Diagnostic fault simulation for synchronous sequential circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Serial diagnostic fault simulation for synchronous sequential circuits.

[BibT_eX]

[DOI]

Integr., 1997

1995

Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization.

[BibT_eX]

[DOI]

Shiann-Rong Kuang

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A fast and memory-efficient diagnostic fault simulation for sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993

Library-Adaptively Integrated Data Path Synthesis for DSP Systems.

[BibT_eX]

[DOI]

Shiann-Rong Kuang

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1990

An Efficient VLSI Switch-Box Router.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1990

1989

A new 3-layer rectilinear area router with obstacle avoidance.

[BibT_eX]

[DOI]