Jeongwon Choe
Orcid: 0000-0002-8386-7704
According to our database1,
Jeongwon Choe
authored at least 12 papers
between 2020 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
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2025
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2025
High-Throughput Software-Defined LDPC Encoder and Decoder With x86-Based Data-Level Parallelism.
IEEE Trans. Veh. Technol., January, 2025
2024
Hard-Decision SCL Polar Decoder With Weighted Pruning Operation for Storage Applications.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Proceedings of the 21st International SoC Design Conference, 2024
Proceedings of the 15th International Conference on Information and Communication Technology Convergence, 2024
2023
A 2.35 Gb/s/mm<sup>2</sup> (7440, 6696) NB-LDPC Decoder over GF(32) using Memory-Reduced Column-Wise Trellis Min-Max Algorithm in 28nm CMOS Technology.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE J. Solid State Circuits, 2022
2021
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A 7Gbps (160, 80) Non-Binary LDPC Decoder with Dual-Message EMS Algorithm in 22nm FinFET Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020