Jeongwon Choe

Orcid: 0000-0002-8386-7704

According to our database1, Jeongwon Choe authored at least 9 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Hard-Decision SCL Polar Decoder With Weighted Pruning Operation for Storage Applications.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2024

2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A 2.35 Gb/s/mm<sup>2</sup> (7440, 6696) NB-LDPC Decoder over GF(32) using Memory-Reduced Column-Wise Trellis Min-Max Algorithm in 28nm CMOS Technology.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

High-Throughput Non-Binary LDPC Decoder Architecture Using Parallel EMS Algorithm.
IEEE J. Solid State Circuits, 2022

2021
FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A 7Gbps (160, 80) Non-Binary LDPC Decoder with Dual-Message EMS Algorithm in 22nm FinFET Technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
Low-Latency Unfolded-KES Architecture for Emerging Storage Class Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020


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