Jeongwon Choe

According to our database, Jeongwon Choe authored at least 10 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Hard-Decision SCL Polar Decoder With Weighted Pruning Operation for Storage Applications.

Dain Park, Dongyun Kam, Sangbu Yun, Jeongwon Choe, Youngjoo Lee

IEEE Trans. Circuits Syst. II Express Briefs, September, 2024

2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications.

Dongyun Kam, Sangbu Yun, Jeongwon Choe, Zhengya Zhang, Namyoon Lee, Youngjoo Lee

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Cost-Efficient Partially-Parallel LDPC Decoder Architecture for 50G-PON Standard.

Jeongwon Choe, Youngjoo Lee

Proceedings of the 21st International SoC Design Conference, 2024

2023

A 2.35 Gb/s/mm² (7440, 6696) NB-LDPC Decoder over GF(32) using Memory-Reduced Column-Wise Trellis Min-Max Algorithm in 28nm CMOS Technology.

Jeongwon Choe, Youngjoo Lee

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm.

Seungwoo Hong, Dongyun Kam, Sangbu Yun, Jeongwon Choe, Namyoon Lee, Youngjoo Lee

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

High-Throughput Non-Binary LDPC Decoder Architecture Using Parallel EMS Algorithm.

Jeongwon Choe, Youngjoo Lee

IEEE J. Solid State Circuits, 2022

2021

FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks.

Changhyeon Kim, Dongyoung Rim, Jeongwon Choe, Dongyun Kam, Giyoon Park, Seokki Kim, Youngjoo Lee

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A 7Gbps (160, 80) Non-Binary LDPC Decoder with Dual-Message EMS Algorithm in 22nm FinFET Technology.

Jeongwon Choe, Youngjoo Lee

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020

Low-Latency Unfolded-KES Architecture for Emerging Storage Class Memories.

Seungsik Moon, Jeongwon Choe, Youngjoo Lee

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm.

Sangbu Yun, Dongyun Kam, Jeongwon Choe, Byeong Yong Kong, Youngjoo Lee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020