Jeonghee Shin

According to our database1, Jeonghee Shin authored at least 10 papers between 2001 and 2012.

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Bibliography

2012
Power management of multi-core chips: Challenges and pitfalls.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Error Tolerance in Server Class Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Floorplanning challenges in early chip planning.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Early chip planning cockpit.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Power-efficient, reliable microprocessor architectures: modeling and design methods.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2008
A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007
A Framework for Architecture-Level Lifetime Reliability Modeling.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

2005
Trends toward on-chip networked microsystems.
Int. J. High Perform. Comput. Netw., 2005

2003
The Performance of Routing Algorithms under Bursty Traffic Loads.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

2001
An SCI-based Software VIA System for PC Clustering.
Proceedings of the 2001 IEEE International Conference on Cluster Computing (CLUSTER 2001), 2001


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