Jeong-Gun Lee
Orcid: 0000-0001-6218-4560
According to our database1,
Jeong-Gun Lee
authored at least 63 papers
between 2000 and 2024.
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Bibliography
2024
Artif. Intell. Rev., September, 2024
Analysis of Transformer's Attention Behavior in Sleep Stage Classification and Limiting It to Improve Performance.
IEEE Access, 2024
Error-Resilient Inference with an Error-Aware Activation Function in a Deep Neural Network.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
Improved Generalization from Limiting Attention in a Transformer for Sleep Stage Classification.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024
2023
Automatic Sleep Stage Classification Using Deep Learning Algorithm for Multi-Institutional Database.
IEEE Access, 2023
2022
Proceedings of the 13th International Conference on Information and Communication Technology Convergence, 2022
2021
Proceedings of the International Conference on Information and Communication Technology Convergence, 2021
Proceedings of the International Conference on Information and Communication Technology Convergence, 2021
2020
In-Situ Timing Error Predictor-Based Two-Cycle Adaptive Frequency Scaling System on an FPGA.
J. Circuits Syst. Comput., 2020
FPGA-Based Multi-Level Approximate Multipliers for High-Performance Error-Resilient Applications.
IEEE Access, 2020
Proceedings of the International Conference on Information and Communication Technology Convergence, 2020
Proceedings of the International Conference on Information and Communication Technology Convergence, 2020
2019
G-DCF: Improving System Spectral Efficiency through Concurrent Transmissions in Wireless LANs.
Wirel. Commun. Mob. Comput., 2019
A Carry Chain-Based ADMFC Design on an FPGA for EMI Reduction and Noise Compensation.
J. Circuits Syst. Comput., 2019
A GALS design based on multi-frequency clocking for digital switching noise reduction.
Integr., 2019
A high-resolution and glitch-free all-digital variable length ring oscillator design on an FPGA.
Comput. Electr. Eng., 2019
Energy-Area-Efficient Approximate Multipliers for Error-Tolerant Applications on FPGAs.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
2018
Analysis of Clock Scheduling in Frequency Domain for Digital Switching Noise Suppressions.
IEEE Trans. Very Large Scale Integr. Syst., 2018
A GALS Design with Opposite-Phase Local Clock Assignment for Power Supply Noise Reduction.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
2017
IEICE Electron. Express, 2017
A performance, power, and energy analysis of ultrasound B-mode imaging on a GPU with VFS.
Concurr. Comput. Pract. Exp., 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2017
2016
Comput. Electr. Eng., 2016
2015
2014
IEICE Trans. Electron., 2014
IEICE Trans. Electron., 2014
Software based ultrasound B-mode/beamforming optimization on GPU and its performance prediction.
Proceedings of the 21st International Conference on High Performance Computing, 2014
2012
Triggering navigators for innovative system design: The case of lab-on-a-chip technology.
Expert Syst. Appl., 2012
Proceedings of the Convergence and Hybrid Information Technology, 2012
Proceedings of the Convergence and Hybrid Information Technology, 2012
2011
IEICE Electron. Express, 2011
Proceedings of the International SoC Design Conference, 2011
Proceedings of the International Conference on IT Convergence and Security, 2011
Proceedings of the Convergence and Hybrid Information Technology, 2011
Proceedings of the Advanced Communication and Networking, 2011
Proceedings of the Intelligent Information and Database Systems, 2011
2010
A Performance/Energy Analysis and Optimization of Multi-Core Architectures with Voltage Scaling Techniques.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
2009
Exploration of Power-Delay Trade-Offs with Heterogeneous Adders by Integer Linear Programming.
J. Circuits Syst. Comput., 2009
IEICE Electron. Express, 2009
An Asymptotic Performance/Energy Analysis and Optimization of Multi-core Architectures.
Proceedings of the Distributed Computing and Networking, 10th International Conference, 2009
2008
Embedding High-Performance Synchronous Routers to Asynchronous Network on Chip.
Proceedings of the 2008 International Conference on Computer Design, 2008
2007
Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions.
J. VLSI Signal Process., 2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007
2005
Instruction level redundant number computations for fast data intensive processing in asynchronous processors.
J. Syst. Archit., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Inf. Syst., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Inf. Syst., 2005
IEICE Trans. Electron., 2005
IEICE Trans. Inf. Syst., 2005
High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
2004
Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004
2003
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units.
Proceedings of the 2003 Design, 2003
Performance optimization of synchronous control units for datapaths with variable delay arithmetic units.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2001
Proceedings of ASP-DAC 2001, 2001
Building a Distributed Asynchronous Control Unit through Automatic Derivation of Hierarchically Decomposed AFSMs from a CDFG.
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001
2000
Automatic distributed asynchronous control circuit generation from data flow graph for asynchronous high-level synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000