Jens Trommer

Orcid: 0000-0003-2972-438X

According to our database1, Jens Trommer authored at least 25 papers between 2013 and 2024.

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Bibliography

2024

REDCAP: Reconfigurable RFET-Based Circuits Against Power Side-Channel Attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Dynamic Reconfigurable Security Cells Based on Emerging Devices Integrable in FDSOI Technology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Formal Analysis of Camouflaged Reconfigurable Circuits.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Single Transistor Analog Building Blocks: Exploiting Back-Bias Reconfigurable Devices.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Evaluation of Schottky barrier height at Silicide/Silicon interface of a Silicon Nanowire with Modulation Acceptor Doped Dielectric Shell.
Proceedings of the Device Research Conference, 2023

Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Special Session: Mitigating Side-Channel Attacks Through Circuit to Application Layer Approaches.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023

2022
Reconfigurable Field Effect Transistors Design Solutions for Delay-Invariant Logic Gates.
IEEE Embed. Syst. Lett., 2022

Compact Modeling of Channel-Resistance Effects in Reconfigurable Field-Effect Transistors.
Proceedings of the 29th International Conference on Mixed Design of Integrated Circuits and System, 2022

Robust Reconfigurable Field Effect Transistors Process Route Enabling Multi-VT Devices Fabrication for Hardware Security Applications.
Proceedings of the Device Research Conference, 2022

2021
END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021

Perspectives on Emerging Computation-in-Memory Paradigms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021


2020
Quantitative Characterization of Reconfigurable Transistor Logic Gates.
IEEE Access, 2020

2019
Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Eliminating Charge Sharing in Clocked Logic Gates on the Device Level Employing Transistors with Multiple Independent Inputs.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

IPCEI subcontracts contributing to 22-FDX Add-On Functionalities at GF.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-Memory.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

2018
A wired-AND transistor: Polarity controllable FET with multiple inputs.
Proceedings of the 76th Device Research Conference, 2018

A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Exploiting transistor-level reconfiguration to optimize combinational circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2014
Reconfigurable silicon nanowire devices and circuits: Opportunities and challenges.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Reconfigurable nanowire electronics - Device principles and circuit prospects.
Proceedings of the European Solid-State Device Research Conference, 2013


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