Jens Rettkowski
According to our database1,
Jens Rettkowski
authored at least 31 papers
between 2014 and 2024.
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Bibliography
2024
Exploration of Power-Savings on Multi-Core Architectures With Offloaded Real-Time Operating System.
IEEE Access, 2024
2021
Design and Programming Methods for Reconfigurable Multi-Core Architectures using a Network-on-Chip-Centric Approach
PhD thesis, 2021
Performance analysis of application-specific instruction-set routers in networks-on-chip.
Proceedings of the NoCArc '21: Proceedings of the 14th International Workshop on Network on Chip Architectures, Virtual Event, Greece, October 18, 2021
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
2020
2019
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019
IP Core Identification in FPGA Configuration Files using Machine Learning Techniques.
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019
2018
Sensor data fusion in the context of electric vehicles charging stations using a Network-on-Chip.
Microprocess. Microsystems, 2018
Comput., 2018
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
2017
J. Parallel Distributed Comput., 2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
HW/SW Co-design of an IEEE 802.11a/g Receiver on Xilinx Zynq SoC using High-Level Synthesis.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017
2016
ACM Trans. Embed. Comput. Syst., 2016
MPSoCSim extension: An OVP simulator for the evaluation of cluster-based multi and many-core architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
RePaBit: Automated generation of relocatable partial bitstreams for Xilinx Zynq FPGAs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Sensor data fusion with MPSoCSim in the context of electric vehicle charging stations.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016
Computation and communication challenges to deploy robots in assisted living environments.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
MPSoCSim: An extended OVP simulator for modeling and evaluation of Network-on-Chip based heterogeneous MPSoCs.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015
Robot navigation based on an efficient combination of an extended A∗ algorithm, bird's eye view and image stitching.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015
A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
2014
RAR-NoC: A reconfigurable and adaptive routable Network-on-Chip for FPGA-based multiprocessor systems.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014